58 lines
7.5 KiB
Markdown
58 lines
7.5 KiB
Markdown
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# 2. Pin Information
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## 2.1 Pin Assignments
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**Figure 5. Pin Assignments – Top View**
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## 2.2 Pin Descriptions
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| Pin Number | Pin Name | Description |
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| --- | --- | --- |
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| Bottom Pad | `GND` | Signal common to the IC. Unless otherwise stated, signals are referenced to the GND pin. GND should also be used as the thermal pad for heat dissipation. |
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| 1 | `CSON` | Battery current sense negative input. Connect to the battery current resistor negative input. Place a ceramic capacitor between CSOP and CSON to provide differential mode filtering. |
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| 2 | `CSOP` | Battery current sense positive input. Connect to the battery current resistor positive input. Place a ceramic capacitor between CSOP and CSON to provide differential mode filtering. |
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| 3 | `VSYS` | Provides feedback voltage for MaxSystemVoltage regulation. |
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| 4 | `BOOT2` | High-side MOSFET Q4 gate driver supply. Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged through an internal boot diode connected from the VDDP to BOOT2 pins. Connect a 0.47µF bootstrap capacitor, which must have an effective capacitance higher than 0.25µF at 5V and x50 effective high-side MOSFET gate capacitance. |
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| 5 | `UGATE2` | High-side MOSFET Q4 gate drive. |
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| 6 | `PHASE2` | Current return path for the high-side MOSFET Q4 gate drive. Connect this pin to the node consisting of the high-side MOSFET Q4 source, the low-side MOSFET Q3 drain, and one terminal of the inductor. |
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| 7 | `LGATE2` | Low-side MOSFET Q3 gate drive. |
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| 8 | `VDDP` | Power supply for the gate drivers. Connect to the VDD pin through a 4.7Ω resistor and connect a 2.2µF (10V) MLCC capacitor to GND. The capacitor must have an effective capacitance higher than 0.4µF at 5V and x1.6 effective capacitance at the BOOT pin at 5V. |
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| Pin Number | Pin Name | Description |
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| --- | --- | --- |
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| 9 | `LGATE1` | Low-side MOSFET Q2 gate drive. |
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| 10 | `PHASE1` | Current return path for the high-side MOSFET Q1 gate drive. Connect this pin to the node consisting of the high-side MOSFET Q1 source, the low-side MOSFET Q2 drain, and one terminal of the inductor. |
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| 11 | `UGATE1` | High-side MOSFET Q1 gate drive. |
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| 12 | `BOOT1` | High-side MOSFET Q1 gate driver supply. Connect an MLCC capacitor across the BOOT1 and PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VDDP to BOOT1 pins. Connect a 0.47µF bootstrap capacitor, which must have an effective capacitance higher than 0.25µF at 5V and x50 effective high-side MOSFET gate capacitance. |
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| 13 | `ASGATE` | Gate drive output to the P-channel adapter FET. The use of ASGATE FETs is optional. If they are not used, leave the ASGATE pin floating. |
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| 14 | `CSIN` | Adapter current sense negative input. |
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| 15 | `CSIP` | Adapter current sense positive input. The modulator also uses the CSIP pin for sensing input voltage in forward mode and output voltage in reverse mode. |
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| 16 | `ADP` | Adapter input used to sense adapter voltage. ASGATE is turned on when the adapter voltage is higher than 3.2V.<br>The ADP pin also provides one of the two internal low power LDO inputs. |
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| 17 | `DCIN` | Internal LDO input that provides power to the IC. Connect a diode OR from the adapter and system outputs. Bypass DCIN with an MLCC capacitor. Connect a 10Ω DCIN resistor between the DCIN pin and the VADP/VSYS diodes, and connect a 4.7µF DCIN capacitor to GND. The capacitor must have an effective capacitance higher than 0.4µF at 30V. |
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| 18 | `VDD` | Internal LDO output that provides the bias power for the internal analog and digital circuit. Connect a 2.2µF (10V) MLCC capacitor to GND. The capacitor must have an effective capacitance higher than 0.4µF at 5V and x1.6 effective capacitance at the BOOT pin at 5V. If VDD is pulled below 2V for more than 1ms, the RAA489118 resets all the SMBus register values to their defaults. |
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| 19 | `ACIN` | Adapter voltage sense. Use a resistor divider externally to detect adapter voltage. The adapter voltage is valid if the ACIN pin voltage is greater than 0.6V. |
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| 20 | `OTGEN/CMIN` | Input pin. OTG function enable pin, stand-alone comparator input pin.<br>When the OTG function is enabled and the general purpose comparator is disabled, pulling this pin high can activate the OTG function.<br>When the general purpose comparator is enabled, this pin is the general purpose comparator input. |
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| 21 | `SDA` | SMBus data I/O. Connect to the data line from the host controller or smart battery. Connect a 10k pull-up resistor according to the SMBus specification. |
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| 22 | `SCL` | SMBus clock I/O. Connect to the clock line from the host controller or smart battery. Connect a 10k pull-up resistor according to the SMBus specification. |
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| 23 | `PROCHOT#` | Open-drain output. Pulled low when ACHOT, DCHOT, or Low_VSYS are detected. IMVP compliant. Send an SMBus command to pull low with OTGCURRENT, BATGONE, ACOK, and the general purpose comparator (see Table 7). |
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| 24 | `ACOK` | Adapter presence indicator output to indicate the adapter is ready. |
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| 25 | `BATGONE` | Input pin to the IC. Logic high on this pin indicates the battery has been removed. Logic low on this pin indicates the battery is present. BATGONE pin logic high forces the BGATE FET to turn off in any circumstances. |
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| 26 | `OTGPG/CMOUT` | Open-drain output. OTG function output power-good indicator or the stand-alone comparator output.<br>When the OTG function is enabled, this signal is low if the OTG output voltage is not within the regulation window.<br>When the OTG function is not used, this signal is the general purpose comparator output. GP comparator must be disabled for OTGPG to function as expected. |
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| Pin Number | Pin Name | Description |
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| --- | --- | --- |
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| 27 | `PROG` | A resistor from the PROG pin to GND sets the following configurations:<br>▪ Default number of the battery cells in series: 2 to 7 cells<br>▪ Autonomous Charging mode: Enabled or disabled<br>See Table 16 for programming options. |
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| 28 | `COMP` | Error amplifier output. Connect a compensation network externally from COMP to GND. |
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| 29 | `AMON/BMON` | Adapter current, OTG output current, battery charging current, or battery discharging current monitor output.<br>▪ V<sub>AMON</sub> = 18x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) for adapter current monitor<br>▪ V<sub>OTGCMON</sub> = 18x (V<sub>CSIN</sub> - V<sub>CSIP</sub>) for OTG output current monitor<br>▪ V<sub>BMON_DISCHARGING</sub> = 18x (V<sub>CSON</sub> - V<sub>CSOP</sub>) for battery discharging current monitor<br>▪ V<sub>BMON_CHARGING</sub> = 36x (V<sub>CSOP</sub> - V<sub>CSON</sub>) for battery charging current monitor |
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| 30 | `CONFIG/PSYS` | CONFIG/PSYS is tied to VDD for Buck-Boost charger configuration without BFET. CONFIG/PSYS is connected to the PSYS resistor for PSYS function for Buck-Boost charger configuration with BFET. Current source output that indicates the platform power consumption.<br>PSYS gain = 0.236µA/W (default) or 0.118µA/W |
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| 31 | `VBAT` | Battery voltage sensor. Used for trickle charging detection and Ideal Diode mode control. Connect an optional ceramic capacitor >1µF from VBAT to GND. The VBAT pin is also one of the two internal low power LDO inputs. |
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| 32 | `BGATE` | Gate drive output to the P-channel FET connecting the system and the battery. This pin can go high to disconnect the battery, low to connect the battery, or operate in Linear mode to maintain the system voltage at the MinSystemVoltage level during trickle charging. |
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