224 lines
20 KiB
Markdown
224 lines
20 KiB
Markdown
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# 7. Modulator Information
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## 7.1 RAA489118 Buck-Boost Charger Modes of Operation
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The RAA489118 buck-boost charger drives an external N-channel MOSFET bridge made of two transistor pairs as shown in Figure 38. The first pair, Q1 and Q2, is a buck arrangement with the transistor center tap connected to an inductor input as is the case with a buck converter. The second transistor pair, Q3 and Q4, is a boost arrangement with the transistor center tap connected to the output of the inductor as is the case with a boost converter. This arrangement supports bucking from a voltage input higher than the battery and also boosting from a voltage input lower than the battery.
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**Table 14. Operation Mode**
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| Mode | Q1 | Q2 | Q3 | Q4 |
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| --- | --- | --- | --- | --- |
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| Buck | Control FET | Sync. FET | OFF | ON |
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| Boost | ON | OFF | Control FET | Sync. FET |
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| Buck-Boost | Control FET | Sync. FET | Control FET | Sync. FET |
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| OTG Buck | ON | OFF | Sync. FET | Control FET |
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| OTG Boost | Sync. FET | Control FET | OFF | ON |
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| OTG Buck-Boost | Sync. FET | Control FET | Sync. FET | Control FET |
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| Pass-Through | ON | OFF | OFF | ON |
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**Figure 38. Buck-Boost Charger Topology**
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The RAA489118 optimizes the Operation mode transition algorithm by comparing the input and output voltage ratio and the load condition. When the adapter voltage V<sub>ADP</sub> is rising and is higher than 91% of the system bus voltage VSYS, the RAA489118 transitions from Boost mode to Buck-Boost mode. If V<sub>ADP</sub> is higher than 114% of VSYS, the RAA489118 forcedly transitions from Buck-Boost mode to Buck mode. At heavier loads, the mode transition point changes accordingly to accommodate the duty cycle change due to the power loss on the charger circuit.
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When the adapter voltage V<sub>ADP</sub> is falling and is lower than 108% of the system bus voltage VSYS, the RAA489118 transitions from Buck mode to Buck-Boost mode. If V<sub>ADP</sub> is lower than 85% of VSYS, the RAA489118 transitions from Buck-Boost mode to Boost mode.
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**Figure 39. Operation Mode**
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When the Force Buck Mode is enabled by setting the Control0 Bit[1] to 1, the RAA489118 operates in Buck mode instead of Buck-Boost mode when VADP is 480mV higher than VSYS. Force Buck mode has a 240mV hysteresis window, so the RAA489118 operates in Buck-Boost mode when VADP is lower than VSYS + 240mV.
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## 7.2 USB On-the-Go (USB OTG)
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When the On-the-Go (OTG) function is enabled with the SMBus command and OTGEN pin, and if the battery voltage V<sub>BAT</sub> is higher than 4.5V, the RAA489118 operates in OTG mode and Control2 Bit[5] controls ASGATE. BATGONE must be low to enable OTG mode.
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When the OTG function is enabled with the SMBus command and OTGEN pin and if the battery voltage V<sub>BAT</sub> is higher than 4.5V, the RAA489118 operates in Reverse Buck, Reverse Boost, or Reverse Buck-Boost mode.
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When the RAA489118 receives the command to enable the OTG function, it starts switching after the debounce time set by Control2 register Bit[13] and Control3 register Bit[0]. When the OTG output voltage reaches the OTG output voltage set by register `0x49` Bit[14:3], OTG power-good OTGPG asserts to high. Control2 register Bit[5] can also be used to turn the ASGATE FET off to cut off the OTG output.
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Before OTG mode starts switching, the CSIP pin voltage needs to drop below the OTG output overvoltage protection threshold (OTG Voltage DAC(`0x49h`) + 1.8V) first. The CSIP pin is the output sensing point in OTG mode.
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The default OTG output voltage is 5.004V. The OTG Voltage register `0x49h` configure the OTG output voltage.
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The default OTG output current is 512mA when R<sub>s1</sub> is 10mΩ. The OTG Current register `0x4Ah` can be used to adjust the OTG output current limit.
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The RAA489118 includes the OTG output undervoltage and overvoltage protection functions. The UVP threshold is OTG output voltage -1.8V and the OVP threshold is OTG output voltage +1.8V.
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When UV is detected, the RAA489118 de-asserts OTGPG. After 32ms, it stops switching and turns off ASGATE. It resumes switching after the debounce time set by Control2 register Bit[13] and Control3 register Bit[0].
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When OV is detected, the RAA489118 de-asserts OTGPG. It resumes switching when the OTG voltage drops below the OTG Voltage DAC value specified at `0x49`.
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BATGONE must be low to enable OTG mode.
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<!-- page 46 -->
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## 7.3 Pass-Through Mode
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Pass-Through Mode (PTM) is configured by Control2 register Bits[1:0]. When PTM (normal or forced) is enabled, the internal reference for the output voltage ramps to the input voltage, and switching continues until the output voltage is within ±150mV of the input (adapter) voltage. Once the output voltage falls within this 300mV window, switching stops, Q1 and Q4 are set on, and Q2 and Q3 are turned off. When PTM is enabled, all protections are still active.
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To disable PTM, set Control2 register Bits[1:0] = 00. On exiting PTM, the internal reference for the output voltage ramps to the MaximumSystemVoltage DAC value, and switching resumes. Normal PTM is also exited if any of the following criteria are encountered:
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- Adapter OV triggers
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- Ideal Diode Mode is entered
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- The battery discharge current exceeds 600mA (for RS2 = 5mΩ)
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- VSYS absolute OV triggers
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Forced PTM can only be exited by disabling PTM using Control2 Bits[1:0].
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Before entering Pass-Through mode, the following is recommended:
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1. Ensure CV mode operation;
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2. Enable slew rate limiting by setting Control6 Bit[6] = 1; and
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3. Change the MaximumSystemVoltage DAC to a value as close to the V<sub>ADP</sub> voltage as possible.
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When Q1 and Q4 are latching on to enter Pass-Through mode, the adapter current limit loop turns on for more than 1ms.
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## 7.4 Modulator Control Loops
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Figure 40 shows the modulator's four main control loops. Each loop has a DAC register to provide settings as needed for each system.
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**Figure 40. Charger Control Loops**
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<!-- page 47 -->
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### 7.4.1 Adapter Current Loop and Two-Level Current Limit
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To set the adapter current limit, write a 16-bit AdapterCurrentLimit1 command to register address `0x3FH` and, optionally, an AdapterCurrentLimit2 command to register address `0x3BH` using the Write-word protocol. See Table 2 for the DAC summary of values.
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The RAA489118 limits the adapter current by limiting the CSIP - CSIN voltage. By using the recommended R<sub>S1</sub> current sense resistor of 10mΩ, the LSB of the register translates to 8mA of adapter current.
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After adapter POR, the AdapterCurrentLimit1 register is reset to the value programmed through the PROG pin resistor. The AdapterCurrentLimit2 register is set to its default value of 1.504A or keeps the value that is written to it previously if the battery is present first. The AdapterCurrentLimit1 and AdapterCurrentLimit2 registers can be read back to verify their content. By default, the two level adapter current limit is disabled.
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The AdapterCurrentLimit2 register has the same specification as the AdapterCurrentLimit1 register.
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The two-level adapter current limit function can be enabled and disabled through SMBus Control2 register Bit[12] and the t1, t2 settings are configured by the Control5 register. When the two-level adapter current limit function is disabled, only the AdapterCurrentLimit1 value is used as the adapter current limit and AdapterCurrentLimit2 value is ignored.
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In a real system, a Turbo event usually does not last very long. It is often no longer than milliseconds, a time length during which the adapter can supply current higher than its DC rating. The RAA489118 uses a two-level adapter current limit to fully take advantage of the surge capability of the adapter and minimize the power drawn from the battery.
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Figure 41 shows the two SMBus programmable adapter current limit levels, AdapterCurrentLimit1 and AdapterCurrentLimit2, as well as the durations t1 and t2. The two-level adapter current limit function is initiated when the adapter current is less than 100mA lower than the AdapterCurrentLimit1 register setting. It starts at AdapterCurrentLimit2 for duration t2, then changes to AdapterCurrentLimit1 for duration t1 before repeating the pattern. These parameters can set the adapter current limit with an envelope that allows the adapter to temporarily output surge current without requiring the charger to enter Turbo mode. This operation maximizes battery life.
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The AdapterCurrentLimit1 register value can be higher or lower than the AdapterCurrentLimit2 value.
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**Figure 41. Two-Level Adapter Current Limit**
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<!-- page 48 -->
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### 7.4.2 USB-PD On-the-Go Output Current
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The OTG output current regulation register DAC (Table 2) contains the SMBus readable and writable current that the current sense loop tries to regulate. This loop reuses the input current sense amplifier. If you are using the USB-PD Programmable Power Supply, this is the current limit loop. *Note*: Renesas recommends disabling OTG undervoltage protection when OTG current limiting mode is anticipated as part of normal operation.
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### 7.4.3 Input Voltage Regulation Loop
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#### 7.4.3.1 Adapter Minimum Voltage
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The input voltage regulation register DAC (Table 2) contains the SMBus readable and writable input voltage limit at which the input voltage loop tries to regulate when the input voltage is dropping. When the ADP is browning out or weak, the input voltage can droop and the input voltage loop tries to regulate to this setting by reducing battery charging current and then system power to try to hold up the input voltage. The system voltage might start to drop if the input power is not high enough to support the system.
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#### 7.4.3.2 USB-PD On-the-Go Minimum Battery Voltage
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The input voltage regulation register DAC (Table 2) sets a minimum voltage for VBAT when operating in OTG mode. Control5 register Bit[11] enables and disables the battery voltage (VBAT) regulation loop. This regulation loop can be used to prevent over-discharging of a battery when operating in OTG mode (for example, USB-PD source mode).
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### 7.4.4 USB-PD On-the-Go Output Voltage
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The OTG output voltage regulation register DAC (Table 2) contains the SMBus readable and writable voltage that the voltage loop tries to regulate. This loop reuses the input voltage sense amp.
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This register accepts any voltage value, but only the valid register bits are written to the register. The maximum value is clamped.
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### 7.4.5 System Voltage Regulation and Trickle Charging
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This loop works with two different voltage settings, MaxSystemVoltage and MinSystemVoltage.
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The MaxSystemVoltage register sets the battery full charging voltage limit. In NVDC charging mode, the MaximumSystemVoltage register setting is also the system bus voltage regulation point when the battery is absent or when the battery is present but not in Charging mode.
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The VSYS pin senses the battery voltage for maximum charging voltage regulation. The VSYS pin is also the system bus voltage regulation sense point.
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If the battery is absent, the BGATE is turned off (no charging) and the system voltage is regulated to the same setting as the MaxSystemVoltage DAC(`0x15h`). To set the maximum charging voltage or the system regulating voltage, write a 16-bit MaxSystemVoltage command to register address `0x15H` using the Write-word protocol shown in Figure 37.
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The RAA489118 supports trickle charging to overly discharged batteries. It can activate the trickle charging function when the battery voltage is lower than MinSystemVoltage setting. The VBAT pin is the battery voltage sense point for Trickle Charge mode.
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To enable Trickle Charging, set the ChargeCurrent register to a non-zero value. To disable trickle charging, set the ChargeCurrent register to 0. See Table 15 for trickle charging control logic.
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The trickle charging current can be programmed to be 1024mA, 512mA, 256mA, or 128mA (with 5mΩ R<sub>s2</sub>) through SMBus Control2 register Bit[15:14] as shown in Table 5.
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In Trickle Charging mode, the RAA489118 regulates the trickle charging current through the buck-boost switcher. Provided that a BFET is present, another independent control loop drives the BFET gate so that the system voltage is maintained at the voltage set in the MinSystemVoltage register. If there is no BFET, the system voltage
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<!-- page 49 -->
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might fall below the MinSystemVoltage setting. The VSYS pin is the system voltage sensing point in Trickle Charging mode.
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When the battery voltage is charged to the MinSystemVoltage register value, the RAA489118 enters Fast Charging mode by limiting the charging current at the ChargeCurrentLimit register setting, which is typically higher than the trickle charge current.
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### 7.4.6 Charging Current Loop
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This loop uses the charge current DAC (see Table 2) to set the fast charging current limit. To set it, write a 16-bit ChargeCurrentLimit command to register address `0x14H` (Table 1).
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The RAA489118 limits the charging current by limiting the CSOP - CSON voltage. Therefore, the charge current depends on the R<sub>s2</sub> resistor value. For example, if the current sense resistor R<sub>s2</sub> is halved, the regulated charge current doubles. By using the current sense resistor R<sub>s2</sub> = 5mΩ, the LSB of the register translates to 8mA of charging current. The ChargeCurrentLimit register accepts any charging current command, but only the valid register bits are written to the register.
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#### 7.4.6.1 Reverse Mode Discharge Current
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When the charger is in reverse mode of operation (OTG), there is a discharge current limit loop that is set by 2x the Charge Current limit register (`0x14`). This discharge current limit loop is in addition to the voltage regulation loop set by the OTG Voltage register, the current limit loop set by the OTG Current register, and the optional VBAT regulation loop set by the Input Voltage register. The discharge current limit loop is disabled when charge current limit (`0x14h`) is zero. When the charge current is a non-zero value, the charger limits the battery discharge current to be less than the discharge current limit (2x the Charge Current limit). This function can be used to limit inrush current from the battery when the OTG Voltage ramps up or down (in addition to the slew rate function).
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### 7.4.7 Turbo Mode Support
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Turbo mode refers to the system drawing more power than the power rating of the adapter.
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If the adapter current reaches the AdapterCurrentLimit1 register set value (or the AdapterCurrentLimit2 register set value, if the two-level adapter current limit function is enabled), or the adapter input voltage drops to the Input Voltage Regulation Reference set by Input Voltage DAC register (`0x4B`), the RAA489118 limits the input power by regulating the adapter current at the AdapterCurrentLimit1/2 register set value, or by regulating the adapter voltage at the Input Voltage Regulation Reference point.
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In Turbo mode, the system bus voltage VSYS drops automatically or the charging current drops automatically to limit the adapter input power. If the VSYS pin voltage is 150mV lower than the VBAT pin voltage, the BGATE FET turns on so that the battery supplies the rest of the power required by the system.
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If the RAA489118 detects 250mA charging current or if the battery discharging current is less than 380mA for longer than the IDM exit timeout (80ms, 40ms, 5ms, or 1 ms), BGATE turns off and Turbo mode exits. The Turbo mode exit timer is configured through Control3 register `0x4C` Bit[8] and Control7 register `0x36` Bit[7]. See Table 15 for BGATE control logic.
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**Table 15. BGATE On/Off Truth Table**
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| Turbo (Control Bit)<br>**0 = Enable**<br>**1 = Disable** | ChargeCurrent Register<br>**0 = Zero**<br>**1 = Nonzero** | BGATE On/Off<br>**System Load Not In Turbo Mode Range** | BGATE On/Off<br>**System Load in Turbo Mode Range** |
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| --- | --- | --- | --- |
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| 0 | 0 | OFF | ON |
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| 0 | 1 | ON for fast charge; Trickle charge is enabled | ON |
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| 1 | 0 | OFF | OFF |
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| 1 | 1 | ON for fast charge; Trickle charge is enabled | ON |
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<!-- page 50 -->
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## 7.5 R3 Modulator
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The RAA489118 uses the patented Renesas Robust Ripple Regulator (R3) modulation scheme. The R3 modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. Figure 42 conceptually shows the R3 modulator circuit, and Figure 43 shows the operation principles in steady state.
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**Figure 42. R3 Modulator**
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**Figure 43. R3 Modulator Operation Principles In Steady State**
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A fixed voltage window (VW window) exists between VW and COMP. The modulator charges the ripple capacitor C<sub>R</sub> with a current source equal to g<sub>m</sub>(V<sub>IN</sub> - V<sub>O</sub>) during PWM on-time and discharges the ripple capacitor C<sub>R</sub> with a current source equal to g<sub>m</sub>V<sub>O</sub> during PWM off-time, where g<sub>m</sub> is a gain factor. The C<sub>R</sub> voltage V<sub>CR</sub> therefore emulates the inductor current waveform. The modulator turns off the PWM pulse when V<sub>CR</sub> reaches VW and turns on the PWM pulse when it reaches COMP.
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Because the modulator works with V<sub>CR</sub>, which is large amplitude and noise free synthesized signal, it achieves lower phase jitter than conventional hysteretic mode modulator.
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Figure 44 shows the operation principles during dynamic response. The COMP voltage rises during dynamic response, turning on PWM pulses earlier and more frequently temporarily, which allows for higher control loop bandwidth than conventional fixed frequency PWM modulators at the same steady state switching frequency.
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<!-- page 51 -->
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**Figure 44. R3 Modulator Operation Principles In Dynamic Response**
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The R3 modulator can operate in Diode Emulation (DE) mode to increase light-load efficiency. In DE mode, the low-side MOSFET conducts when the current is flowing from source-to-drain and does not allow reverse current, which emulates a diode. As shown in Figure 45, when LGATE is on, the low-side MOSFET carries current and creates negative voltage on the phase node due to the voltage drop across the ON-resistance. The IC monitors the current by monitoring the phase node voltage. It turns off LGATE when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss.
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**Figure 45. Diode Emulation**
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If the load current is light enough, as Figure 45 shows, the inductor current reaches and stays at zero before the next phase node pulse, and the regulator is in Discontinuous Conduction Mode (DCM). If the load current is heavy enough, the inductor current never reaches 0A, and the regulator is in Continuous Conduction Mode (CCM) although the controller is in DE mode.
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Figure 46 shows the operation principle in DE mode at light load. The load gets incrementally lighter in the three cases from top to bottom. The PWM on-time is determined by the VW window size and therefore is the same, so the inductor current triangle is the same in the three cases. The R3 modulator clamps the ripple capacitor voltage V<sub>CR</sub> in DE mode to mimic the inductor current. The COMP voltage takes longer to reach V<sub>CR</sub>, which naturally stretches the switching period. The inductor current triangles move farther apart from each other so that the inductor current average value is equal to the load current. The reduced switching frequency helps increase light-load efficiency.
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