# RAA489400 Datasheet — Table of Contents

Markdown transcription of `REN_RAA489400_DST_20240827.pdf` (Renesas RAA489400
USB Type-C Port Controller), Rev.1.00, Aug 27 2024, document `R16DS0292EU0100`.

The datasheet was split into the per-chapter PDFs in this folder; each has a
matching `.md` transcription and, where the chapter contains figures, a folder
of extracted PNGs. Page numbers below are the printed datasheet pages, and are
mirrored in the transcriptions as `<!-- page N -->` markers.

## Chapters

| # | Chapter | Pages | Source PDF | Figures |
|---|---|---|---|---|
| 1 | [Overview](01-overview.md) | 5–10 | [pdf](01-overview.pdf) | 9 |
| 2 | [Pin Information](02-pin-information.md) | 11–13 | [pdf](02-pin-information.pdf) | 1 |
| 3 | [Specifications](03-specifications.md) | 14–19 | [pdf](03-specifications.pdf) | — |
| 4 | [Typical Performance Graphs](04-typical-performance-graphs.md) | 20 | [pdf](04-typical-performance-graphs.pdf) | 2 |
| 5 | [Functional Description](05-functional-description.md) | 21–30 | [pdf](05-functional-description.pdf) | 1 |
| 6 | [General SMBus/I²C Architecture](06-general-smbus-i2c-architecture.md) | 31–33 | [pdf](06-general-smbus-i2c-architecture.pdf) | 11 |
| 7 | [Registers](07-registers.md) | 34–78 | [pdf](07-registers.pdf) | — |
| 8 | [Layout](08-layout.md) | 79 | [pdf](08-layout.pdf) | 1 |
| 9–11 | [Package, Ordering, Revision History](09-11-package-ordering-revision.md) | 80 | [pdf](09-11-package-ordering-revision.pdf) | — |

## Sections

- [1. Overview](01-overview.md#1-overview)
  - [1.1 Block Diagram](01-overview.md#11-block-diagram)
  - [1.2 Typical Application](01-overview.md#12-typical-application)
- [2. Pin Information](02-pin-information.md#2-pin-information)
  - [2.1 Pin Assignments](02-pin-information.md#21-pin-assignments)
  - [2.2 Pin Descriptions](02-pin-information.md#22-pin-descriptions)
  - [2.3 Unused Pin Termination](02-pin-information.md#23-unused-pin-termination)
- [3. Specifications](03-specifications.md#3-specifications)
  - [3.1 Absolute Maximum Ratings](03-specifications.md#31-absolute-maximum-ratings)
  - [3.2 Recommended Operating Conditions](03-specifications.md#32-recommended-operating-conditions)
  - [3.3 Thermal Specifications](03-specifications.md#33-thermal-specifications)
  - [3.4 Electrical Specifications](03-specifications.md#34-electrical-specifications)
  - [3.5 SMBus Timing Specification](03-specifications.md#35-smbus-timing-specification)
- [4. Typical Performance Graphs](04-typical-performance-graphs.md#4-typical-performance-graphs)
- [5. Functional Description](05-functional-description.md#5-functional-description)
  - [5.1 Start-Up](05-functional-description.md#51-start-up)
  - [5.2 Programming Resistors](05-functional-description.md#52-programming-resistors)
  - [5.3 USB Type-C Port Controller Interface](05-functional-description.md#53-usb-type-c-port-controller-interface)
    - [5.3.1 USB PD BMC PHY](05-functional-description.md#531-usb-pd-bmc-phy)
    - [5.3.2 USB Type-C Current Mode](05-functional-description.md#532-usb-type-c-current-mode)
    - [5.3.3 VCONN Mux](05-functional-description.md#533-vconn-mux)
    - [5.3.4 Source Path Control](05-functional-description.md#534-source-path-control)
    - [5.3.5 Sink Path Control](05-functional-description.md#535-sink-path-control)
    - [5.3.6 Bi-directional VBUS Source and Sink Path Control](05-functional-description.md#536-bi-directional-vbus-source-and-sink-path-control)
    - [5.3.7 VBUS Monitoring and Measurement](05-functional-description.md#537-vbus-monitoring-and-measurement)
    - [5.3.8 Internal Sink Path Discharge](05-functional-description.md#538-internal-sink-path-discharge)
    - [5.3.9 Initial Sink Fast Role Swap](05-functional-description.md#539-initial-sink-fast-role-swap)
  - [5.4 Protection Features](05-functional-description.md#54-protection-features)
    - [5.4.1 VBUS Overcurrent Protection](05-functional-description.md#541-vbus-overcurrent-protection)
    - [5.4.2 VBUS Overvoltage Protection](05-functional-description.md#542-vbus-overvoltage-protection)
    - [5.4.3 VBUS Source Undervoltage Protection](05-functional-description.md#543-vbus-source-undervoltage-protection)
    - [5.4.4 VBUS Source Reverse Voltage Protection](05-functional-description.md#544-vbus-source-reverse-voltage-protection)
    - [5.4.5 VCONN Overcurrent Protection](05-functional-description.md#545-vconn-overcurrent-protection)
    - [5.4.6 VCONN Overvoltage Protection](05-functional-description.md#546-vconn-overvoltage-protection)
    - [5.4.7 VCONN Undervoltage Protection](05-functional-description.md#547-vconn-undervoltage-protection)
    - [5.4.8 VCONN Over-temperature Protection](05-functional-description.md#548-vconn-over-temperature-protection)
    - [5.4.9 VCONN Reverse Voltage Protection](05-functional-description.md#549-vconn-reverse-voltage-protection)
  - [5.5 OCP# Output](05-functional-description.md#55-ocp-output)
  - [5.6 PROCHOT#](05-functional-description.md#56-prochot)
  - [5.7 GPIO](05-functional-description.md#57-gpio)
    - [5.7.1 Overcurrent Input](05-functional-description.md#571-overcurrent-input)
  - [5.8 Clock Management](05-functional-description.md#58-clock-management)
- [6. General SMBus/I²C Architecture](06-general-smbus-i2c-architecture.md#6-general-smbusi²c-architecture)
  - [6.1 Data Validity](06-general-smbus-i2c-architecture.md#61-data-validity)
  - [6.2 START and STOP Conditions](06-general-smbus-i2c-architecture.md#62-start-and-stop-conditions)
  - [6.3 Acknowledge (ACK)](06-general-smbus-i2c-architecture.md#63-acknowledge-ack)
  - [6.4 Writing Single Byte Registers](06-general-smbus-i2c-architecture.md#64-writing-single-byte-registers)
  - [6.5 Reading Single Byte Registers](06-general-smbus-i2c-architecture.md#65-reading-single-byte-registers)
  - [6.6 Writing Two-Byte Registers](06-general-smbus-i2c-architecture.md#66-writing-two-byte-registers)
  - [6.7 Reading Two-Byte Registers](06-general-smbus-i2c-architecture.md#67-reading-two-byte-registers)
  - [6.8 Writing the TRANSMIT_BUFFER](06-general-smbus-i2c-architecture.md#68-writing-the-transmit_buffer)
  - [6.9 Reading the RECEIVE_BUFFER](06-general-smbus-i2c-architecture.md#69-reading-the-receive_buffer)
  - [6.10 Reading the Alert Response Address](06-general-smbus-i2c-architecture.md#610-reading-the-alert-response-address)
- [7. Registers](07-registers.md#7-registers)
  - [7.1 Register Map](07-registers.md#71-register-map) — full `00h`–`FFh` address map
  - [7.2 Register Descriptions](07-registers.md#72-register-descriptions) — 63 registers, `VENDOR_ID` (`00h`) through `TYPE_C_PRAMETER` (`E2h`)
- [8. Layout](08-layout.md#8-layout)
- [9. Package Outline Drawing](09-11-package-ordering-revision.md#9-package-outline-drawing)
- [10. Ordering Information](09-11-package-ordering-revision.md#10-ordering-information)
- [11. Revision History](09-11-package-ordering-revision.md#11-revision-history)

## Figures

| # | Title | Image | In chapter |
|---|---|---|---|
| 1 | Block Diagram | [png](01-overview/figure-01.png) | [1.1](01-overview.md#11-block-diagram) |
| 2 | Typical USB-C Application, TCPC + TCPM, DRP — VBUS SNK up to 48V, SRC up to 5V | [png](01-overview/figure-02.png) | [1.2](01-overview.md#12-typical-application) |
| 3 | Typical USB-C Application, Source Only — VBUS SRC up to 5V | [png](01-overview/figure-03.png) | [1.2](01-overview.md#12-typical-application) |
| 4 | Typical USB-C Application, Sink Only — VBUS SNK up to 48V | [png](01-overview/figure-04.png) | [1.2](01-overview.md#12-typical-application) |
| 5 | Typical USB-C Application, DRP with GPIO Control | [png](01-overview/figure-05.png) | [1.2](01-overview.md#12-typical-application) |
| 6 | Typical USB-C Application, Source Only with GPIO Control | [png](01-overview/figure-06.png) | [1.2](01-overview.md#12-typical-application) |
| 7 | Typical USB-C Application, Sink Only with GPIO Control | [png](01-overview/figure-07.png) | [1.2](01-overview.md#12-typical-application) |
| 8 | USB-C Application, DRP with `VSNK_GATE` + GPIO Control — SNK/SRC up to 48V | [png](01-overview/figure-08.png) | [1.2](01-overview.md#12-typical-application) |
| 9 | USB-C Application, Bi-directional DRP with GPIO Control — SNK/SRC up to 48V | [png](01-overview/figure-09.png) | [1.2](01-overview.md#12-typical-application) |
| 10 | Pin Assignments – Top View | [png](02-pin-information/figure-10.png) | [2.1](02-pin-information.md#21-pin-assignments) |
| 11 | Startup VSYS33 Powered (2.0ms/Div, 2.0V/Div) | [png](04-typical-performance-graphs/figure-11.png) | [4](04-typical-performance-graphs.md#4-typical-performance-graphs) |
| 12 | Startup from VBUS | [png](04-typical-performance-graphs/figure-12.png) | [4](04-typical-performance-graphs.md#4-typical-performance-graphs) |
| 13 | Typical Multiport Sink Only | [png](05-functional-description/figure-13.png) | [5.3.6](05-functional-description.md#536-bi-directional-vbus-source-and-sink-path-control) |
| 14 | General SMBus Architecture | [png](06-general-smbus-i2c-architecture/figure-14.png) | [6](06-general-smbus-i2c-architecture.md#6-general-smbusi²c-architecture) |
| 15 | Data Validity | [png](06-general-smbus-i2c-architecture/figure-15.png) | [6.1](06-general-smbus-i2c-architecture.md#61-data-validity) |
| 16 | Start and Stop Waveforms | [png](06-general-smbus-i2c-architecture/figure-16.png) | [6.2](06-general-smbus-i2c-architecture.md#62-start-and-stop-conditions) |
| 17 | Acknowledge on the SMBus | [png](06-general-smbus-i2c-architecture/figure-17.png) | [6.3](06-general-smbus-i2c-architecture.md#63-acknowledge-ack) |
| 18 | Writing Single Byte Registers | [png](06-general-smbus-i2c-architecture/figure-18.png) | [6.4](06-general-smbus-i2c-architecture.md#64-writing-single-byte-registers) |
| 19 | Reading Single Byte Registers | [png](06-general-smbus-i2c-architecture/figure-19.png) | [6.5](06-general-smbus-i2c-architecture.md#65-reading-single-byte-registers) |
| 20 | Writing Two-Byte Registers | [png](06-general-smbus-i2c-architecture/figure-20.png) | [6.6](06-general-smbus-i2c-architecture.md#66-writing-two-byte-registers) |
| 21 | Reading Two-Byte Registers | [png](06-general-smbus-i2c-architecture/figure-21.png) | [6.7](06-general-smbus-i2c-architecture.md#67-reading-two-byte-registers) |
| 22 | Writing the `TRANSMIT_BUFFER` | [png](06-general-smbus-i2c-architecture/figure-22.png) | [6.8](06-general-smbus-i2c-architecture.md#68-writing-the-transmit_buffer) |
| 23 | Reading the `RECEIVE_BUFFER` | [png](06-general-smbus-i2c-architecture/figure-23.png) | [6.9](06-general-smbus-i2c-architecture.md#69-reading-the-receive_buffer) |
| 24 | Reading the Alert Response Address | [png](06-general-smbus-i2c-architecture/figure-24.png) | [6.10](06-general-smbus-i2c-architecture.md#610-reading-the-alert-response-address) |
| — | *(untitled current-sensing trace routing drawing)* | [png](08-layout/current-sensing-trace-routing.png) | [8](08-layout.md#8-layout) |

The last entry is unnumbered and untitled in the source: it is drawn inside the
`CSIN`/`CSIP` cell of the layout-guidelines table rather than being a captioned
figure, so it has no figure number or caption to quote.

## Known issues in the source datasheet

These were transcribed verbatim rather than silently corrected:

- **§3.4** — "SRC 5V VBUS Overvoltage Rising Threshold" is printed with unit
  **mV** but has values 5.8 / 6.3 / 6.6, which only make sense as volts.
- **§7.1** — Table 7 cites "Table 57" for both `GPIO_OC_EN` (`89h`) and
  `VBUS_CTRL` (`90h`), and skips Table 59.
- **§7.2.6** — the `ALERT` bit B9 (Fault) description is cut off mid-sentence
  in the printed page: "A fault has occurred in".
- **§7.2.49** — `VBUS_CTRL` bits 10:8 (`N4`) show a reset of `0000b` for a
  3-bit field.
- **§7.2.63** — spelled `TYPE_C_PRAMETER` in the section heading but
  `TYPE_C_PARAMETER` in Table 72. Other typos kept as printed:
  `TIME_INTERVALif`, `POWER_COTNROL`, `VBUS_PEAK_CURRENTare`,
  `SNK_TO_SRC_TIMERON`.
- **§8** — the `NC` row lists pins `1, 7, 17, 23`, but the same table assigns
  pin 7 to `GPIO2` and pin 23 to `VSRC_BOOT`.
- **§9** — contains no package outline drawing or dimension table; it only
  points to the end of the full datasheet and the Renesas website.

## Transcription notes

- GitHub-flavored Markdown has no `rowspan`, so vertically merged cells in the
  source are repeated on each row.
- Tables that break across a page in the source are kept split, with their
  printed "(Cont.)" captions, so the `<!-- page N -->` markers stay in order.
- Figures were extracted from the vector PDFs by
  [`tools/extract-figures.py`](../tools/extract-figures.py); run it inside
  `nix develop`.