add REN_RAA489118

REN_RAA489118/00-features-applications.md

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+
+# RAA489118
+
+Buck-Boost Battery Charger with SMBus Interface for General 30V and USB PD EPR
+
+The RAA489118 is a buck-boost charger supporting 30V input and 30V battery. The RAA489118 provides charging and protection features for power tools, portable vacuums, battery-powered lawn mowers, power banks, and additional system bus regulation for notebooks. It also supports any USB-C interface platform including USB PD EPR. The advanced Renesas R3™ technology provides highly efficient light-load operation and fast transient response.
+
+In Charging mode, the RAA489118 accepts input power from a wide range of DC power sources (such as conventional AC/DC charger adapters, USB PD ports, and travel adapters) and safely charges battery packs with up to 7 serially connected battery cells up to 30V. The device can operate with only a battery, only an adapter, or with both connected.
+
+The RAA489118 supports reverse buck, reverse boost, or reverse buck-boost operation to the input port from 2-cell to 7-cell batteries.
+
+The RAA489118 provides programming resistor options including autonomous charging, max output voltages, adapter current limit. Additionally, it provides serial communication that enables programming of many critical parameters to deliver a customized solution.
+
+## Features
+
+- Buck-boost charger for 2 to 7-cell up to 30V batteries
+- Optional BFET
+- Input voltage range: 3.9V to 30V (no dead zone)
+- System output voltage: 2.4V to 30.8V
+- Autonomous charging option (automatic completion of charging)
+- Pass-Through mode in forward direction
+- Adapter current and battery current monitor (AMON/BMON)
+- Trickle charging of depleted battery
+- Reverse buck, boost, and buck-boost operation from battery
+- Battery Ship mode option
+- 4×4 32 Ld TQFN package compatible with the ISL9238/RAA489108 family of parts
+
+## Applications
+
+- Standalone battery charging for 2 to 7-cell batteries, including batteries for power tools, portable vacuums, battery-powered lawn mowers, drones
+- 2-cell to 7-cell tablets, Ultrabooks, notebooks, power banks, and any USB-C interface portable device requiring batteries
+
+**Figure 1. Full-Featured Architecture Solutions Enabled by RAA489118**
+
+![Figure 1. Full-Featured Architecture Solutions Enabled by RAA489118](00-features-applications/figure-01.png)

REN_RAA489118/01-overview.md

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+
+# 1. Overview
+
+## 1.1 Typical Application Diagram
+
+**Figure 2. Typical Application Circuit #1 (Battery Charging Only with No BFET)**
+
+![Figure 2. Typical Application Circuit #1 (Battery Charging Only with No BFET)](01-overview/figure-02.png)
+
+<!-- page 5 -->
+
+**Figure 3. Typical Application Circuit #2 (NVDC Charging with a BFET)**
+
+![Figure 3. Typical Application Circuit #2 (NVDC Charging with a BFET)](01-overview/figure-03.png)
+
+<!-- page 6 -->
+
+## 1.2 Block Diagram
+
+**Figure 4. Block Diagram**
+
+![Figure 4. Block Diagram](01-overview/figure-04.png)

REN_RAA489118/02-pin-information.md

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+
+# 2. Pin Information
+
+## 2.1 Pin Assignments
+
+**Figure 5. Pin Assignments – Top View**
+
+![Figure 5. Pin Assignments – Top View](02-pin-information/figure-05.png)
+
+## 2.2 Pin Descriptions
+
+| Pin Number | Pin Name | Description |
+| --- | --- | --- |
+| Bottom Pad | `GND` | Signal common to the IC. Unless otherwise stated, signals are referenced to the GND pin. GND should also be used as the thermal pad for heat dissipation. |
+| 1 | `CSON` | Battery current sense negative input. Connect to the battery current resistor negative input. Place a ceramic capacitor between CSOP and CSON to provide differential mode filtering. |
+| 2 | `CSOP` | Battery current sense positive input. Connect to the battery current resistor positive input. Place a ceramic capacitor between CSOP and CSON to provide differential mode filtering. |
+| 3 | `VSYS` | Provides feedback voltage for MaxSystemVoltage regulation. |
+| 4 | `BOOT2` | High-side MOSFET Q4 gate driver supply. Connect an MLCC capacitor across the BOOT2 and PHASE2 pins. The boot capacitor is charged through an internal boot diode connected from the VDDP to BOOT2 pins. Connect a 0.47µF bootstrap capacitor, which must have an effective capacitance higher than 0.25µF at 5V and x50 effective high-side MOSFET gate capacitance. |
+| 5 | `UGATE2` | High-side MOSFET Q4 gate drive. |
+| 6 | `PHASE2` | Current return path for the high-side MOSFET Q4 gate drive. Connect this pin to the node consisting of the high-side MOSFET Q4 source, the low-side MOSFET Q3 drain, and one terminal of the inductor. |
+| 7 | `LGATE2` | Low-side MOSFET Q3 gate drive. |
+| 8 | `VDDP` | Power supply for the gate drivers. Connect to the VDD pin through a 4.7Ω resistor and connect a 2.2µF (10V) MLCC capacitor to GND. The capacitor must have an effective capacitance higher than 0.4µF at 5V and x1.6 effective capacitance at the BOOT pin at 5V. |
+
+<!-- page 8 -->
+
+| Pin Number | Pin Name | Description |
+| --- | --- | --- |
+| 9 | `LGATE1` | Low-side MOSFET Q2 gate drive. |
+| 10 | `PHASE1` | Current return path for the high-side MOSFET Q1 gate drive. Connect this pin to the node consisting of the high-side MOSFET Q1 source, the low-side MOSFET Q2 drain, and one terminal of the inductor. |
+| 11 | `UGATE1` | High-side MOSFET Q1 gate drive. |
+| 12 | `BOOT1` | High-side MOSFET Q1 gate driver supply. Connect an MLCC capacitor across the BOOT1 and PHASE1 pins. The boot capacitor is charged through an internal boot diode connected from the VDDP to BOOT1 pins. Connect a 0.47µF bootstrap capacitor, which must have an effective capacitance higher than 0.25µF at 5V and x50 effective high-side MOSFET gate capacitance. |
+| 13 | `ASGATE` | Gate drive output to the P-channel adapter FET. The use of ASGATE FETs is optional. If they are not used, leave the ASGATE pin floating. |
+| 14 | `CSIN` | Adapter current sense negative input. |
+| 15 | `CSIP` | Adapter current sense positive input. The modulator also uses the CSIP pin for sensing input voltage in forward mode and output voltage in reverse mode. |
+| 16 | `ADP` | Adapter input used to sense adapter voltage. ASGATE is turned on when the adapter voltage is higher than 3.2V.<br>The ADP pin also provides one of the two internal low power LDO inputs. |
+| 17 | `DCIN` | Internal LDO input that provides power to the IC. Connect a diode OR from the adapter and system outputs. Bypass DCIN with an MLCC capacitor. Connect a 10Ω DCIN resistor between the DCIN pin and the VADP/VSYS diodes, and connect a 4.7µF DCIN capacitor to GND. The capacitor must have an effective capacitance higher than 0.4µF at 30V. |
+| 18 | `VDD` | Internal LDO output that provides the bias power for the internal analog and digital circuit. Connect a 2.2µF (10V) MLCC capacitor to GND. The capacitor must have an effective capacitance higher than 0.4µF at 5V and x1.6 effective capacitance at the BOOT pin at 5V. If VDD is pulled below 2V for more than 1ms, the RAA489118 resets all the SMBus register values to their defaults. |
+| 19 | `ACIN` | Adapter voltage sense. Use a resistor divider externally to detect adapter voltage. The adapter voltage is valid if the ACIN pin voltage is greater than 0.6V. |
+| 20 | `OTGEN/CMIN` | Input pin. OTG function enable pin, stand-alone comparator input pin.<br>When the OTG function is enabled and the general purpose comparator is disabled, pulling this pin high can activate the OTG function.<br>When the general purpose comparator is enabled, this pin is the general purpose comparator input. |
+| 21 | `SDA` | SMBus data I/O. Connect to the data line from the host controller or smart battery. Connect a 10k pull-up resistor according to the SMBus specification. |
+| 22 | `SCL` | SMBus clock I/O. Connect to the clock line from the host controller or smart battery. Connect a 10k pull-up resistor according to the SMBus specification. |
+| 23 | `PROCHOT#` | Open-drain output. Pulled low when ACHOT, DCHOT, or Low_VSYS are detected. IMVP compliant. Send an SMBus command to pull low with OTGCURRENT, BATGONE, ACOK, and the general purpose comparator (see Table 7). |
+| 24 | `ACOK` | Adapter presence indicator output to indicate the adapter is ready. |
+| 25 | `BATGONE` | Input pin to the IC. Logic high on this pin indicates the battery has been removed. Logic low on this pin indicates the battery is present. BATGONE pin logic high forces the BGATE FET to turn off in any circumstances. |
+| 26 | `OTGPG/CMOUT` | Open-drain output. OTG function output power-good indicator or the stand-alone comparator output.<br>When the OTG function is enabled, this signal is low if the OTG output voltage is not within the regulation window.<br>When the OTG function is not used, this signal is the general purpose comparator output. GP comparator must be disabled for OTGPG to function as expected. |
+
+<!-- page 9 -->
+
+| Pin Number | Pin Name | Description |
+| --- | --- | --- |
+| 27 | `PROG` | A resistor from the PROG pin to GND sets the following configurations:<br>▪ Default number of the battery cells in series: 2 to 7 cells<br>▪ Autonomous Charging mode: Enabled or disabled<br>See Table 16 for programming options. |
+| 28 | `COMP` | Error amplifier output. Connect a compensation network externally from COMP to GND. |
+| 29 | `AMON/BMON` | Adapter current, OTG output current, battery charging current, or battery discharging current monitor output.<br>▪ V<sub>AMON</sub> = 18x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) for adapter current monitor<br>▪ V<sub>OTGCMON</sub> = 18x (V<sub>CSIN</sub> - V<sub>CSIP</sub>) for OTG output current monitor<br>▪ V<sub>BMON_DISCHARGING</sub> = 18x (V<sub>CSON</sub> - V<sub>CSOP</sub>) for battery discharging current monitor<br>▪ V<sub>BMON_CHARGING</sub> = 36x (V<sub>CSOP</sub> - V<sub>CSON</sub>) for battery charging current monitor |
+| 30 | `CONFIG/PSYS` | CONFIG/PSYS is tied to VDD for Buck-Boost charger configuration without BFET. CONFIG/PSYS is connected to the PSYS resistor for PSYS function for Buck-Boost charger configuration with BFET. Current source output that indicates the platform power consumption.<br>PSYS gain = 0.236µA/W (default) or 0.118µA/W |
+| 31 | `VBAT` | Battery voltage sensor. Used for trickle charging detection and Ideal Diode mode control. Connect an optional ceramic capacitor >1µF from VBAT to GND. The VBAT pin is also one of the two internal low power LDO inputs. |
+| 32 | `BGATE` | Gate drive output to the P-channel FET connecting the system and the battery. This pin can go high to disconnect the battery, low to connect the battery, or operate in Linear mode to maintain the system voltage at the MinSystemVoltage level during trickle charging. |

REN_RAA489118/03-specifications.md

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+
+# 3. Specifications
+
+## 3.1 Absolute Maximum Ratings
+
+*Caution*: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
+
+| Parameter | Minimum | Maximum | Unit |
+| --- | --- | --- | --- |
+| `CSIP`, `CSIN`, `DCIN`, `ADP`, `ASGATE` | -0.3 | +36 | V |
+| `DCIN` - `VDD` | -0.3 | +31 | V |
+| `PHASE1` | GND - 0.3 | +36 | V |
+| `PHASE1` | GND - 2 (<20ns) | +36 | V |
+| `BOOT1`, `UGATE1` | GND - 0.3 | VDDP+36 | V |
+| `PHASE2` | GND - 0.3 | 36 | V |
+| `PHASE2` | GND - 2 (<20ns) | 36 | V |
+| `BOOT2`, `UGATE2` | GND - 0.3 | VDDP+36 | V |
+| `LGATE1`, `LGATE2` | GND - 0.3 | +6.5 | V |
+| `LGATE1`, `LGATE2` | GND - 2 (<20ns) | +6.5 | V |
+| `VBAT`, `VSYS`, `CSOP`, `CSON`, `BGATE` | -0.3 | +36 | V |
+| `VDD`, `VDDP` | -0.3 | +6.5 | V |
+| `COMP` | -0.3 | +6.5 | V |
+| `AMON/BMON`, `PSYS` | -0.3 | +6.5 | V |
+| `OTGEN`, `BATGONE` | -0.3 | +6.5 | V |
+| `ACIN`, `PROCHOT#`, `OTGPG`, `ACOK` | -0.3 | +6.5 | V |
+| `SCL`, `SDA` | -0.3 | +6.5 | V |
+| `BOOT1` - `PHASE1`, `BOOT2` - `PHASE2` | -0.3 | +6.5 | V |
+| `CSIP` - `CSIN`, `CSOP` - `CSON` | -0.3 | +0.3 | V |
+| `OTGPG`, `PROCHOT#`, `ACOK` | - | 2 | mA |
+| Junction Temperature Range (T<sub>J</sub>) | -10 | +125 | °C |
+| Storage Temperature Range (T<sub>S</sub>) | -65 | +175 | °C |
+| Human Body Model (Tested per JS-001-2023) | - | 2 | kV |
+| Charged Device Model (Tested per JS-002-2022) | - | 750 | V |
+| Latch-Up (Tested per JESD78E; Class 2, Level A) | - | 100 | mA |
+
+## 3.2 Recommended Operating Conditions
+
+| Parameter | Parameter | Minimum | Maximum | Unit |
+| --- | --- | --- | --- | --- |
+| Ambient Temperature | RAA489118ARGNP | -10 | +100 | °C |
+| Ambient Temperature | RAA489118A3GNP | -40 | +100 | °C |
+| Junction Temperature | RAA489118ARGNP | -10 | +125 | °C |
+| Junction Temperature | RAA489118A3GNP | -40 | +125 | °C |
+| Adapter Voltage | | +4 | +30 | V |
+
+<!-- page 11 -->
+
+## 3.3 Thermal Specifications
+
+| Parameter | Package | Symbol | Conditions | Typical Value | Unit |
+| --- | --- | --- | --- | --- | --- |
+| Thermal Resistance | 32 Ld TQFN Package | θ<sub>JA</sub><sup>[1]</sup> | Junction to ambient. | 38 | °C/W |
+| Thermal Resistance | 32 Ld TQFN Package | θ<sub>JC</sub><sup>[2]</sup> | Junction to case. | 2.5 | °C/W |
+
+1. θ<sub>JA</sub> is measured in free air with the component mounted on a high-effective thermal conductivity test board with direct attach features. See TB379.
+2. For θ<sub>JC</sub>, the case temperature location is the center of the exposed metal pad on the package underside.
+
+## 3.4 Electrical Specifications
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.**
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| **UVLO/ACOK** | | | | | | |
+| VADP UVLO Rising | `VADP_UVLO_r` | - | **3.05** | 3.4 | **3.7** | V |
+| VADP UVLO Hysteresis<sup>[2]</sup> | `VADP_UVLO_h` | - | - | 600 | - | mV |
+| V<sub>BAT</sub> UVLO Rising | `VBAT_UVLO_r` | - | **2.30** | 2.45 | **2.65** | V |
+| V<sub>BAT</sub> UVLO Hysteresis | `VBAT_UVLO_h` | - | - | 400 | - | mV |
+| V<sub>BAT</sub> 4P5V Rising | `VBAT_4P5_r` | - | **4.25** | 4.50 | **4.90** | V |
+| V<sub>BAT</sub> 4P5V Hysteresis | `VBAT_4P5_h` | - | - | 400 | - | mV |
+| VDD 2P7 POR Falling, SMBus and BGATE/BMON Active Threshold | `VDD_2P7_f` | - | **2.5** | 2.7 | **2.9** | V |
+| VDD 2P7 POR Hysteresis<sup>[2]</sup> | `VDD_2P7_h` | - | - | 150 | - | mV |
+| VDD 3P8 POR Rising, Modulator and Gate Driver Active | `VDD_3P8_r` | - | **3.6** | 3.8 | **3.9** | V |
+| VDD 3P8 POR Hysteresis | `VDD_3P8_h` | - | - | 140 | - | mV |
+| ACIN Rising | `ACIN_r` | - | **0.58** | 0.6 | **0.615** | V |
+| ACIN Hysteresis | `ACIN_h` | - | - | 50 | - | mV |
+| **Linear Regulator** | | | | | | |
+| VDD Output Voltage | `VDD` | 6V < V<sub>DCIN</sub> < 30V | **4.5** | 5.0 | **5.5** | V |
+| VDD Dropout Voltage | `VDD_dp` | <35mA, V<sub>DCIN</sub> = 4V | - | - | **200** | mV |
+| VDD Overcurrent Threshold | `VDD_OC` | ARGNP Junction Temperature: -10 to +125°C | **85** | 115 | **145** | mA |
+| VDD Overcurrent Threshold | `VDD_OC` | A3GNP Junction Temperature: -40 to +125°C | **85** | 115 | **155** | mA |
+
+<!-- page 12 -->
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.** (Cont.)
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| Battery Current | I<sub>BAT1</sub> | Battery only, BGATE OFF, PSYS OFF, GPC OFF, BMON OFF, V<sub>BAT</sub> = 29.4V, DCIN current comes from battery, I<sub>BAT</sub> = I<sub>VBAT</sub> + I<sub>CSOP</sub> + I<sub>CSON</sub> + I<sub>DCIN</sub> + I<sub>VSYS</sub> | - | 24 | **50** | µA |
+| Battery Current | I<sub>BAT2</sub> | Battery only, BGATE ON, PSYS OFF, GPC OFF, BMON ON, V<sub>BAT</sub> = 29.4V, DCIN current comes from battery, I<sub>BAT</sub> = I<sub>VBAT</sub> + I<sub>CSOP</sub> + I<sub>CSON</sub> + I<sub>DCIN</sub> + I<sub>VSYS</sub> | - | 74 | - | µA |
+| Battery Current | I<sub>BAT3</sub> | Battery only, BGATE on, PSYS ON, BMON OFF, V<sub>BAT</sub> = 29.4V, DCIN current comes from battery, I<sub>BAT</sub> = I<sub>VBAT</sub> + I<sub>CSOP</sub> + I<sub>CSON</sub> + I<sub>DCIN</sub> + I<sub>VSYS</sub> | - | 925 | **1155** | µA |
+| **Adapter Current Regulation, R<sub>s1</sub> = 10mΩ** | | | | | | |
+| Adapter Current Accuracy | - | CSIP - CSIN = 50mV | - | 5 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 50mV | **-2.2** | - | **2.2** | % |
+| Adapter Current Accuracy | - | CSIP - CSIN = 40mV | - | 4 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 40mV | **-2.5** | - | **2.5** | % |
+| Adapter Current Accuracy | - | CSIP - CSIN = 30mV | - | 3 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 30mV | **-3.5** | - | **3.5** | % |
+| Adapter Current Accuracy | - | CSIP - CSIN = 25mV | - | 2.5 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 25mV | **-4.2** | - | **4.2** | % |
+| Adapter Current Accuracy | - | CSIP - CSIN = 20mV | - | 2 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 20mV | **-5.0** | - | **5.0** | % |
+| Adapter Current Accuracy | - | CSIP - CSIN = 15mV | - | 1.5 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 15mV | **-6.9** | - | **6.9** | % |
+| Adapter Current Accuracy | - | CSIP - CSIN = 10mV | - | 1 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 10mV | **-10** | - | **10** | % |
+| Adapter Current Accuracy | - | CSIP - CSIN = 5mV | - | 0.5 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 5mV | **-20** | - | **20** | % |
+| Adapter Current Accuracy | - | CSIP - CSIN = 2.5mV | - | 0.25 | - | A |
+| Adapter Current Accuracy | - | CSIP - CSIN = 2.5mV | **-40** | - | **40** | % |
+| Adapter Current PROCHOT# Threshold R<sub>s1</sub> = 10mΩ | I<sub>ADP_HOT_TH10</sub> | ACProchot = `0x0B00H` (5.632A) | - | 5.632 | - | A |
+| Adapter Current PROCHOT# Threshold R<sub>s1</sub> = 10mΩ | I<sub>ADP_HOT_TH10</sub> | ACProchot = `0x0B00H` (5.632A) | **-1.5** | - | **1.5** | % |
+| Adapter Current PROCHOT# Threshold R<sub>s1</sub> = 10mΩ | I<sub>ADP_HOT_TH10</sub> | ACProchot = `0x0500H` (2.56A) | - | 2.56 | - | A |
+| Adapter Current PROCHOT# Threshold R<sub>s1</sub> = 10mΩ | I<sub>ADP_HOT_TH10</sub> | ACProchot = `0x0500H` (2.56A) | **-2.5** | - | **2.5** | % |
+| Adapter Current PROCHOT# Threshold R<sub>s1</sub> = 10mΩ | I<sub>ADP_HOT_TH10</sub> | ACProchot = `0x0400H` (2.048A) | - | 2.048 | - | A |
+| Adapter Current PROCHOT# Threshold R<sub>s1</sub> = 10mΩ | I<sub>ADP_HOT_TH10</sub> | ACProchot = `0x0400H` (2.048A) | **-4** | - | **4** | % |
+| Adapter Current PROCHOT# Threshold R<sub>s1</sub> = 10mΩ | I<sub>ADP_HOT_TH10</sub> | ACProchot = `0x0200H` (1.024A) | - | 1.024 | - | A |
+| Adapter Current PROCHOT# Threshold R<sub>s1</sub> = 10mΩ | I<sub>ADP_HOT_TH10</sub> | ACProchot = `0x0200H` (1.024A) | **-6** | - | **6** | % |
+
+<!-- page 13 -->
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.** (Cont.)
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| **System Voltage Regulation** | | | | | | |
+| Maximum System Voltage Accuracy | - | MaxSystemVoltage for 8.4V and 12.6V | **-1.0** | - | **1.0** | % |
+| Maximum System Voltage Accuracy | - | MaxSystemVoltage for 16.8V and 21V | **-0.75** | - | **0.75** | % |
+| Maximum System Voltage Accuracy | - | MaxSystemVoltage for 25.2V and 29.4V | **-0.5** | - | **0.5** | % |
+| Minimum System Voltage Accuracy | - | VDAC = 5V to 25V | **-3** | - | **3** | % |
+| Input Voltage Regulation Accuracy | - | Input Voltage Register = 4.096V | **3.92** | - | **4.18** | V |
+| **Charge Current Regulation, R<sub>s2</sub> = 5mΩ (Limits apply across temperature range of 0°C to +85°C)** | | | | | | |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 30mV | - | 6 | - | A |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 30mV | **-3.5** | - | **3.5** | % |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 25mV | - | 5 | - | A |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 25mV | **-3.85** | - | **3.85** | % |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 20mV | - | 4 | - | A |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 20mV | **-4** | - | **4** | % |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 15mV | - | 3 | - | A |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 15mV | **-5.2** | - | **5.2** | % |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 10mV | - | 2 | - | A |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 10mV | **-6** | - | **6** | % |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 5mV | - | 1 | - | A |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 5mV | **-12** | - | **12** | % |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 2.5mV | - | 0.5 | - | A |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 2.5mV | **-22.2** | - | **22.2** | % |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 1.28mV | - | 0.256 | - | A |
+| Charge Current Accuracy | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 1.28mV | **-42** | - | **42** | % |
+| **BGATE Clamp** | | | | | | |
+| VSYS - VBGATE ON | - | Charging enabled | **7.45** | 8.30 | **9.05** | V |
+| VSYS - VBGATE OFF | - | Charging disabled | - | 0 | - | V |
+| **ASGATE Clamp** | | | | | | |
+| VADP - VASGATE ON | - | | - | 10 | - | V |
+| VADP - VASGATE OFF | - | | - | 0 | - | V |
+| **Trickle Charging Current Regulation, R<sub>s2</sub> = 5mΩ (Limits apply across temperature range of 0°C to +85°C)** | | | | | | |
+| Trickle Charge Current Accuracy | - | Trickle, 1024mA | **938** | 1024 | **1109** | mA |
+| Trickle Charge Current Accuracy | - | Trickle, 512mA | **410** | 512 | **614** | mA |
+| Trickle Charge Current Accuracy | - | Trickle, 256mA | **180** | 256 | **360** | mA |
+| Trickle Charge Current Accuracy | - | Trickle, 128mA | **55** | 128 | **192** | mA |
+| Fast Charge to Trickle Charge Threshold | - | V<sub>SYS</sub> - V<sub>BGATE</sub> | **4.5** | 5.05 | **5.6** | V |
+
+<!-- page 14 -->
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.** (Cont.)
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| Trickle Charge to Fast Charge Threshold Hysteresis | - | V<sub>SYS</sub> - V<sub>BGATE</sub> | **50** | 130 | **290** | mV |
+| Fast Charge to Trickle Charge BGATE Threshold<sup>[2]</sup> | - | V<sub>SYS</sub> > 7V, V<sub>FB</sub> >> V<sub>REF</sub> | - | 1.15 | - | V |
+| Trickle Charge to Fast Charge BGATE Threshold Hysteresis<sup>[2]</sup> | - | V<sub>SYS</sub> > 7V, V<sub>FB</sub> >> V<sub>REF</sub> | - | 50 | - | mV |
+| **Ideal Diode Mode** | | | | | | |
+| Entering Ideal Diode Mode VSYS Voltage Threshold | - | BGATE off, VSYS falling<br>V<sub>BAT</sub> - V<sub>CSON</sub> | **100** | 150 | **200** | mV |
+| Exiting Ideal Diode Mode Battery Discharging Current Threshold | - | R<sub>s2</sub> = 5mΩ | **190** | 380 | **550** | mA |
+| Exiting Ideal Diode Mode Battery Charging Current Threshold | - | R<sub>s2</sub> = 5mΩ | **150** | 250 | **350** | mA |
+| BGATE Source | - | V<sub>SYS</sub> - V<sub>BGATE</sub> = 2V, charging disabled | **4** | 5 | **10** | mA |
+| BGATE Sink | - | V<sub>BGATE</sub> - V<sub>GND</sub> = 2V, charging enabled | **20** | 30 | **40** | µA |
+| BGATE Sink | - | V<sub>BGATE</sub> - V<sub>GND</sub> = 2V, in Ideal Diode mode | - | 9 | - | mA |
+| **AMON/BMON** | | | | | | |
+| **Input Current Sense Amplifier, R<sub>s1</sub> = 10mΩ** | | | | | | |
+| CSIP/CSIN Input Voltage Range<sup>[2]</sup> | - | - | **4** | - | **30** | V |
+| Forward AMON Gain | - | - | - | 18.01 | - | V/V |
+| Forward AMON Accuracy V<sub>AMON</sub> = 18.01 x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) | - | V<sub>CSIP</sub> - V<sub>CSIN</sub> = 50mV (5A), V<sub>CSIP</sub> = 5V, 28V | **-2.8** | - | **2.8** | % |
+| Forward AMON Accuracy V<sub>AMON</sub> = 18.01 x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) | - | V<sub>CSIP</sub> - V<sub>CSIN</sub> = 10mV (1A), V<sub>CSIP</sub> = 5V, 28V | **-10** | - | **10** | % |
+| Forward AMON Accuracy V<sub>AMON</sub> = 18.01 x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) | - | V<sub>CSIP</sub> - V<sub>CSIN</sub> = 5mV (0.5A), V<sub>CSIP</sub> = 5V, 28V | **-16.8** | - | **16.8** | % |
+| Forward AMON Accuracy V<sub>AMON</sub> = 18.01 x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) | - | V<sub>CSIP</sub> - V<sub>CSIN</sub> = 1mV (0.1A), V<sub>CSIP</sub> = 5V, 28V | **-78.8** | - | **78.8** | % |
+| Reverse AMON Gain | - | - | - | 17.9 | - | V/V |
+| Reverse AMON Accuracy V<sub>AMON</sub> = 17.9 x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) | - | V<sub>CSIN</sub> - V<sub>CSIP</sub> = 40mV (4A), V<sub>CSIP</sub> = 5V, 28V | **-4.5** | - | **4.5** | % |
+| Reverse AMON Accuracy V<sub>AMON</sub> = 17.9 x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) | - | V<sub>CSIN</sub> - V<sub>CSIP</sub> = 10mV (1A), V<sub>CSIP</sub> = 5V, 28V | **-12.6** | - | **13.5** | % |
+| Reverse AMON Accuracy V<sub>AMON</sub> = 17.9 x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) | - | V<sub>CSIN</sub> - V<sub>CSIP</sub> = 5mV (0.5A), V<sub>CSIP</sub> = 5V, 28V | **-25.5** | - | **25.5** | % |
+| Reverse AMON Accuracy V<sub>AMON</sub> = 17.9 x (V<sub>CSIP</sub> - V<sub>CSIN</sub>) | - | V<sub>CSIN</sub> - V<sub>CSIP</sub> = 2.56mV (0.256A), V<sub>CSIP</sub> = 5V, 28V | **-48.5** | - | **48.5** | % |
+
+<!-- page 15 -->
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.** (Cont.)
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| AMON Minimum Output Voltage | - | V<sub>CSIP</sub> - V<sub>CSIN</sub> = 0V | - | - | **30** | mV |
+| **Discharge Current Sense Amplifier, R<sub>s2</sub> = 5mΩ** | | | | | | |
+| BMON Gain (Battery Discharging) | - | - | - | 17.97 | - | V/V |
+| BMON Accuracy V<sub>BMON</sub> = 17.97×(V<sub>CSON</sub> - V<sub>CSOP</sub>) | - | V<sub>CSON</sub> - V<sub>CSOP</sub> = 50mV (10A), V<sub>CSON</sub> = 8V, 29.4V | **-3.5** | - | **3.1** | % |
+| BMON Accuracy V<sub>BMON</sub> = 17.97×(V<sub>CSON</sub> - V<sub>CSOP</sub>) | - | V<sub>CSON</sub> - V<sub>CSOP</sub> = 10mV (2A), V<sub>CSON</sub> = 8V, 29.4V | **-11.5** | - | **6** | % |
+| BMON Accuracy V<sub>BMON</sub> = 17.97×(V<sub>CSON</sub> - V<sub>CSOP</sub>) | - | V<sub>CSON</sub> - V<sub>CSOP</sub> = 5mV (1A), V<sub>CSON</sub> = 8V, 29.4V | **-23** | - | **14** | % |
+| BMON Accuracy V<sub>BMON</sub> = 17.97×(V<sub>CSON</sub> - V<sub>CSOP</sub>) | - | V<sub>CSON</sub> - V<sub>CSOP</sub> = 3mV (0.6A), V<sub>CSON</sub> = 8V, 29.4V | **-39** | - | **22.1** | % |
+| **Charge Current Sense Amplifier, R<sub>s2</sub> = 5mΩ (Limits apply across the temperature range of 0°C to +85°C)** | | | | | | |
+| BMON Gain (Battery Charging) | - | - | - | 36.07 | - | V/V |
+| BMON Accuracy V<sub>BMON</sub> = 36.07 x (V<sub>CSOP</sub> - V<sub>CSON</sub>) | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 30mV (6A), V<sub>CSON</sub> = 8V, 29.4V | **-5** | - | **5** | % |
+| BMON Accuracy V<sub>BMON</sub> = 36.07 x (V<sub>CSOP</sub> - V<sub>CSON</sub>) | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 20mV (4A), V<sub>CSON</sub> = 8V, 29.4V | **-5.9** | - | **5.9** | % |
+| BMON Accuracy V<sub>BMON</sub> = 36.07 x (V<sub>CSOP</sub> - V<sub>CSON</sub>) | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 5mV (1A), V<sub>CSON</sub> = 8V, 29.4V | **-13.9** | - | **13.9** | % |
+| BMON Accuracy V<sub>BMON</sub> = 36.07 x (V<sub>CSOP</sub> - V<sub>CSON</sub>) | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 2.5mV (0.5A), V<sub>CSON</sub> = 8V, 29.4V | **-24.6** | - | **24.6** | % |
+| BMON Accuracy V<sub>BMON</sub> = 36.07 x (V<sub>CSOP</sub> - V<sub>CSON</sub>) | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 1.28mV (0.256A), V<sub>CSON</sub> = 8V, 29.4V | **-45** | - | **45** | % |
+| BMON Minimum Output Voltage | - | V<sub>CSOP</sub> - V<sub>CSON</sub> = 0V | - | - | **31** | mV |
+| Discharging Current PROCHOT# Threshold, R<sub>s2</sub> = 5mΩ | I<sub>DIS_HOT_TH</sub> | DCProchot# = 2.048A | **1.77** | 2.08 | **2.39** | A |
+| Discharging Current PROCHOT# Threshold, Battery Only, R<sub>s2</sub> = 5mΩ | I<sub>DIS_HOT_TH</sub> | DCProchot# = 12A | **10.6** | 12.9 | **15.2** | A |
+| Discharging Current PROCHOT# Threshold, Battery Only, R<sub>s2</sub> = 5mΩ | I<sub>DIS_HOT_TH</sub> | DCProchot# = 6A | **5.2** | 6.5 | **8** | A |
+| AMON/BMON Source Resistance<sup>[2]</sup> | - | - | - | - | **5** | Ω |
+| AMON/BMON Sink Resistance<sup>[2]</sup> | - | - | - | - | **5** | Ω |
+| **BATGONE and OTGEN** | | | | | | |
+| High-Level Input Voltage | - | - | **0.9** | - | - | V |
+| Low-Level Input Voltage | - | - | - | - | **0.4** | V |
+| Pull-Down Current | - | `BATGONE` and `OTGEN` = 5V | - | 5 | - | µA |
+
+<!-- page 16 -->
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.** (Cont.)
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| **PROCHOT#** | | | | | | |
+| PROCHOT# Debounce Time | - | `Control2` register `Bit[10:9]` = `11` | **0.85** | 1 | **1.15** | ms |
+| PROCHOT# Debounce Time | - | `Control2` register `Bit[10:9]` = `10` | **425** | 500 | **575** | µs |
+| PROCHOT# Duration Time | - | `Control2` register `Bit[8:6]` = `000` | **8.5** | 10 | **11.5** | ms |
+| PROCHOT# Duration Time | - | `Control2` register `Bit[8:6]` = `001` | **17** | 20 | **23** | ms |
+| Low VSYS PROCHOT# Trip Threshold | V<sub>LOW_VSYS_HOT</sub> | `Control1` register `Bit[1:0]` = `00` | **5.8** | 6.0 | **6.2** | V |
+| Low VSYS PROCHOT# Trip Threshold | V<sub>LOW_VSYS_HOT</sub> | `Control1` register `Bit[1:0]` = `01` | **6.1** | 6.3 | **6.5** | V |
+| Low VSYS PROCHOT# Trip Threshold | V<sub>LOW_VSYS_HOT</sub> | `Control1` register `Bit[1:0]` = `10` | **6.4** | 6.6 | **6.8** | V |
+| Low VSYS PROCHOT# Trip Threshold | V<sub>LOW_VSYS_HOT</sub> | `Control1` register `Bit[1:0]` = `11` | **6.7** | 6.9 | **7.1** | V |
+| **PSYS with NVDC Charger Configuration when `CONFIG/PSYS` Is Not Tied High<sup>[2]</sup>** | | | | | | |
+| PSYS Output Current<br>R<sub>s1</sub> = 10mΩ<br>R<sub>s2</sub> = 5mΩ | I<sub>PSYS</sub><br>`Control3` `Bit[9]` = `0`<br>I<sub>PSYS</sub> = 0.236µA/W × Power + 0µA | V<sub>CSIP</sub> = 28V, V<sub>CSIP</sub> - V<sub>CSIN</sub> = 40mV,<br>V<sub>BAT</sub> = 12V, 29.4V,<br>V<sub>CSOP</sub> - V<sub>CSON</sub> = -10mV | **-5** | - | **5** | % |
+| PSYS Output Current<br>R<sub>s1</sub> = 10mΩ<br>R<sub>s2</sub> = 5mΩ | I<sub>PSYS</sub><br>`Control3` `Bit[9]` = `1`<br>I<sub>PSYS</sub> = 0.118µA/W ×Power | V<sub>CSIP</sub> = 28V, V<sub>CSIP</sub> - V<sub>CSIN</sub> = 80mV,<br>V<sub>BAT</sub> = 12V, 29.4V,<br>V<sub>CSOP</sub> - V<sub>CSON</sub> = -20mV | **-5** | - | **5** | % |
+| Maximum PSYS Output Voltage | V<sub>PSYS_MAX</sub> | - | **3** | - | - | V |
+| **Buck-Boost Charger Configuration without BFET when `CONFIG/PSYS` is Tied High** | | | | | | |
+| Comparator at `CONFIG/PSYS`[2] | - | - | - | VDD-0.7V | - | V |
+| **OTG** | | | | | | |
+| OTG Voltage | - | `OTGVoltage` register = 5.004V | **4.9** | 5.03 | **5.15** | V |
+| OTG Current | - | `OTGCurrent` register = 512mA,<br>(`OTGVoltage` = 5.004V, 29.4V) | **373** | 512 | **675** | mA |
+| OTG Current | - | `OTGCurrent` register = 1024mA,<br>(`OTGVoltage` = 5.004V, 29.4V) | **870** | 1024 | **1200** | mA |
+| OTG Current | - | `OTGCurrent` register = 1536mA,<br>(`OTGVoltage` = 5.004V, 29.4V) | **1370** | 1536 | **1726** | mA |
+| OTG Current | - | `OTGCurrent` register = 3072mA,<br>(`OTGVoltage` = 5.004V, 29.4V) | **2841** | 3072 | **3314** | mA |
+| OTG Current | - | `OTGCurrent` register = 4096mA,<br>(`OTGVoltage` = 5.004V, 29.4V) | **3858** | 4096 | **4350** | mA |
+| **General Purpose Comparator** | | | | | | |
+| General Purpose Comparator Rising Threshold | - | Reference = 1.2V | **1.11** | 1.2 | **1.32** | V |
+| General Purpose Comparator Rising Threshold | - | Reference = 2V | **1.93** | 2 | **2.1** | V |
+| General Purpose Comparator Hysteresis | - | Reference = 1.2V | - | 45 | - | mV |
+| General Purpose Comparator Hysteresis | - | Reference = 2V | - | 45 | - | mV |
+
+<!-- page 17 -->
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.** (Cont.)
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| **Protection** | | | | | | |
+| VSYS Absolute Overvoltage Rising Threshold | - | - | 32.2 | 33.6 | 34.3 | V |
+| VSYS Absolute Overvoltage Hysteresis<sup>[2]</sup> | - | - | - | 540 | - | mV |
+| VSYS Overvoltage Rising Threshold | - | `MaxSystemVoltage` register value = 8.4V | **9.68** | 10 | **10.27** | V |
+| VSYS Overvoltage Rising Threshold | - | `MaxSystemVoltage` register value = 29.4V | **30.6** | 31 | **31.6** | V |
+| VSYS Overvoltage Hysteresis | - | `MaxSystemVoltage` register value = 8.4V | **550** | 790 | **1045** | mV |
+| VSYS Overvoltage Hysteresis | - | `MaxSystemVoltage` register value = 29.4V | **600** | 850 | **1100** | mV |
+| VSYS UV Falling Threshold | - | `Control6` register `Bit[2:0]` = `001` | - | 3 | - | V |
+| VSYS UV Falling Threshold | - | `Control6` register `Bit[2:0]` = `010` | - | 3.9 | - | V |
+| VSYS UV Falling Threshold | - | `Control6` register `Bit[2:0]` = `011` | - | 4.8 | - | V |
+| VSYS UV Falling Threshold | - | `Control6` register `Bit[2:0]` = `100` | - | 5.7 | - | V |
+| VSYS UV Falling Threshold | - | `Control6` register `Bit[2:0]` = `101` | - | 6.6 | - | V |
+| VSYS UV Falling Threshold | - | `Control6` register `Bit[2:0]` = `110` | - | 7.5 | - | V |
+| VSYS UV Falling Threshold | - | `Control6` register `Bit[2:0]` = `111` | - | 8.4 | - | V |
+| VSYS OK Threshold | - | - | **0.45** | 0.6 | **0.75** | V |
+| VSYS OK Source Current | - | - | - | 10 | - | mA |
+| Over-Temperature Threshold<sup>[2]</sup> | - | - | **140** | 150 | **160** | °C |
+| Adapter Overvoltage Rising Threshold | - | - | **32.2** | 33.3 | **33.95** | V |
+| Adapter Overvoltage Hysteresis | - | - | **390** | 590 | **760** | mV |
+| OTG Undervoltage Falling Threshold | - | OTG voltage = 5.004V | **2.85** | 3.2 | **3.65** | V |
+| OTG Undervoltage Rising Hysteresis<sup>[2]</sup> | - | OTG voltage = 5.004V | - | 0.9 | - | V |
+| OTG Overvoltage Rising Threshold | - | OTG voltage = 5.004V | **6.4** | 6.8 | **7.2** | V |
+| OTG Overvoltage Falling Hysteresis<sup>[2]</sup> | - | OTG voltage = 5.004V | - | 0.9 | - | V |
+| **Oscillator** | | | | | | |
+| Oscillator Frequency, Digital Core Only | - | - | **0.85** | 1 | **1.15** | MHz |
+| Digital Debounce Time Accuracy<sup>[2]</sup> | - | - | **-15** | - | **15** | % |
+| **Miscellaneous** | | | | | | |
+| Switching Frequency Accuracy | - | COMP > 1.7V and not in period stretching | **-15** | - | **15** | % |
+
+<!-- page 18 -->
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.** (Cont.)
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| Battery Learn Mode Auto-Exit Threshold | - | `MinSystemVoltage` = 5.376V<br>`Control1` register `Bit[13]` = `1` | **5.05** | 5.35 | **5.7** | V |
+| Battery Learn Mode Auto-Exit Hysteresis | - | `MinSystemVoltage` = 5.376V<br>`Control1` register `Bit[13]` = `1` | - | 330 | - | mV |
+| ADP Discharge Current | - | ADP = 5V to 32V | - | 10 | - | mA |
+| VSYS Discharge Current | - | VSYS = 5V to 30.8V | - | 10 | - | mA |
+| **SMBus** | | | | | | |
+| SDA/SCL Input Low Voltage | - | - | - | - | **0.6** | V |
+| SDA/SCL Input High Voltage | - | - | **1.3** | - | - | V |
+| SDA/SCL Input Bias Current | - | - | - | - | **1** | µA |
+| SDA, Output Sink Current | - | `SDA` = 0.4V | **4** | - | - | mA |
+| SMBus Frequency | f<sub>SMB</sub> | - | **10** | - | **400** | kHz |
+| **Gate Driver<sup>[2]</sup>** | | | | | | |
+| UGATE1 Pull-Up Resistance | UG1<sub>RPU</sub> | 100mA source current | - | 800 | **1200** | mΩ |
+| UGATE1 Source Current | UG1<sub>SRC</sub> | `UGATE1` - `PHASE1` = 2.5V | **1.3** | 2 | - | A |
+| UGATE1 Pull-Down Resistance | UG1<sub>RPD</sub> | 100mA sink current | - | 350 | **475** | mΩ |
+| UGATE1 Sink Current | UG1<sub>SNK</sub> | `UGATE1` - `PHASE1` = 2.5V | **1.9** | 2.8 | - | A |
+| LGATE1 Pull-Up Resistance | LG1<sub>RPU</sub> | 100mA source current | - | 800 | **1200** | mΩ |
+| LGATE1 Source Current | LG1<sub>SRC</sub> | `LGATE1` - `GND` = 2.5V | **1.3** | 2 | - | A |
+| LGATE1 Pull-Down Resistance | LG1<sub>RPD</sub> | 100mA sink current | - | 300 | **450** | mΩ |
+| LGATE1 Sink Current | LG1<sub>SNK</sub> | `LGATE1` - `GND` = 2.5V | **2.3** | 3.5 | - | A |
+| LGATE2 Pull-Up Resistance | LG2<sub>RPU</sub> | 100mA source current | - | 800 | **1200** | mΩ |
+| LGATE2 Source Current | LG2<sub>SRC</sub> | `LGATE2` - `GND` = 2.5V | **1.3** | 2 | - | A |
+| LGATE2 Pull-Down Resistance | LG2<sub>RPD</sub> | 100mA sink current | - | 300 | **450** | mΩ |
+| LGATE2 Sink Current | LG2<sub>SNK</sub> | `LGATE2` - `GND` = 2.5V | **2.3** | 3.5 | - | A |
+| UGATE2 Pull-Up Resistance | UG2<sub>RPU</sub> | 100mA source current | - | 800 | **1200** | mΩ |
+| UGATE2 Source Current | UG2<sub>SRC</sub> | `UGATE2` - `PHASE2` = 2.5V | **1.3** | 2 | - | A |
+| UGATE2 Pull-Down Resistance | UG2<sub>RPD</sub> | 100mA sink current | - | 350 | **475** | mΩ |
+| UGATE2 Sink Current | UG2<sub>SNK</sub> | `UGATE2` - `PHASE2` = 2.5V | **1.9** | 2.8 | - | A |
+| UGATE1 to LGATE1 Dead Time | t<sub>UG1LG1DEAD</sub> | - | **10** | 20 | **40** | ns |
+
+<!-- page 19 -->
+
+Operating conditions: ADP = CSIP = CSIN = 5V and 28V, VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.
+**Boldface limits apply across the junction temperature range, -40°C to +125°C unless otherwise specified.** (Cont.)
+
+| Parameter | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| LGATE1 to UGATE1 Dead Time | t<sub>LG1UG1DEAD</sub> | - | **10** | 20 | **40** | ns |
+| LGATE2 to UGATE2 Dead Time | t<sub>LG2UG2DEAD</sub> | - | **10** | 20 | **40** | ns |
+| UGATE2 to LGATE2 Dead Time | t<sub>UG2LG2DEAD</sub> | - | **10** | 20 | **40** | ns |
+
+1. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
+2. Values or limits established by characterization and are not production tested.
+
+## 3.5 SMBus Timing Specification
+
+| Parameters | Symbol | Test Conditions | Min<sup>[1]</sup> | Typ | Max<sup>[1]</sup> | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| SMBus Frequency | F<sub>SMB</sub> | - | 10 | - | 400 | kHz |
+| Bus Free Time | t<sub>BUF</sub> | - | 4.7 | - | - | µs |
+| Start Condition Hold Time from SCL | t<sub>HD:STA</sub> | - | 4 | - | - | µs |
+| Start Condition Set-Up Time from SCL | t<sub>SU:STA</sub> | - | 4.7 | - | - | µs |
+| Stop Condition Set-Up Time from SCL | t<sub>SU:STO</sub> | - | 4 | - | - | µs |
+| SDA Hold Time from SCL | t<sub>HD:DAT</sub> | - | 300 | - | - | ns |
+| SDA Set-Up Time from SCL | t<sub>SU:DAT</sub> | - | 250 | - | - | ns |
+| SCL Low Period | t<sub>LOW</sub> | - | 4.7 | - | - | µs |
+| SCL High Period | t<sub>HIGH</sub> | - | 4 | - | - | µs |
+| SMBus Inactivity Timeout | - | Maximum charging period without a SMBus Write to `MaxSystemVoltage` or `ChargeCurrent` register | - | 175 | - | s |
+
+1. Limits established by characterization and are not production tested.
+
+<!-- page 20 -->
+
+## 3.6 Gate Driver Timing Diagrams
+
+**Figure 6. Gate Driver Timing Diagram**
+
+![Figure 6. Gate Driver Timing Diagram](03-specifications/figure-06.png)

REN_RAA489118/04-typical-performance-graphs.md

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+<!-- page 21 -->
+
+# 4. Typical Performance Graphs
+
+## 4.1 Battery Charging Only (No BFET)
+
+**Figure 7. Adapter Insertion, V<sub>ADP</sub>: 0V → 5V, V<sub>BAT</sub> = 18V, ChargeCurrent = 0.256A**
+
+![Figure 7. Adapter Insertion, VADP: 0V → 5V, VBAT = 18V, ChargeCurrent = 0.256A](04-typical-performance-graphs/figure-07.png)
+
+**Figure 8. Adapter Insertion, V<sub>ADP</sub>: 0V → 5V, V<sub>BAT</sub> = 18V, ChargeCurrent = 0.256A (Figure 7 Zoomed In)**
+
+![Figure 8. Adapter Insertion, VADP: 0V → 5V, VBAT = 18V, ChargeCurrent = 0.256A (Figure 7 Zoomed In)](04-typical-performance-graphs/figure-08.png)
+
+**Figure 9. Adapter Removal, V<sub>ADP</sub>: 28V → 0V, V<sub>BAT</sub> = 18V, ChargeCurrent = 6A**
+
+![Figure 9. Adapter Removal, VADP: 28V → 0V, VBAT = 18V, ChargeCurrent = 6A](04-typical-performance-graphs/figure-09.png)
+
+**Figure 10. Adapter Voltage Ramp Up, Boost → Buck-Boost → Buck Operation Mode Transitions**
+
+![Figure 10. Adapter Voltage Ramp Up, Boost → Buck-Boost → Buck Operation Mode Transitions](04-typical-performance-graphs/figure-10.png)
+
+**Figure 11. Adapter Voltage Ramp Down, Buck → Buck-Boost → Boost Operation Mode Transitions**
+
+![Figure 11. Adapter Voltage Ramp Down, Buck → Buck-Boost → Boost Operation Mode Transitions](04-typical-performance-graphs/figure-11.png)
+
+<!-- page 22 -->
+
+**Figure 12. Boost Mode: Charge Current Loop to Adapter Current Loop, V<sub>ADP</sub> = 5V, V<sub>BAT</sub> = 16V, AdapterCurrentLimit = 3A, ChargeCurrent: 0.5A → 1A**
+
+![Figure 12. Boost Mode: Charge Current Loop to Adapter Current Loop, VADP = 5V, VBAT = 16V, AdapterCurrentLimit = 3A, ChargeCurrent: 0.5A → 1A](04-typical-performance-graphs/figure-12.png)
+
+**Figure 13. Buck_Boost Mode: Charge Current Loop to Adapter Current Loop, V<sub>ADP</sub> = 20V, V<sub>BAT</sub> = 19V, AdapterCurrentLimit = 5A, ChargeCurrent: 2A → 6A Buck_Boost_CCM_stretch_period = 2x**
+
+![Figure 13. Buck_Boost Mode: Charge Current Loop to Adapter Current Loop, VADP = 20V, VBAT = 19V, AdapterCurrentLimit = 5A, ChargeCurrent: 2A → 6A Buck_Boost_CCM_stretch_period = 2x](04-typical-performance-graphs/figure-13.png)
+
+**Figure 14. Buck Mode: Charge Current Loop to Adapter Current Loop, V<sub>ADP</sub> = 28V, V<sub>BAT</sub> = 22V, AdapterCurrentLimit = 5A, ChargeCurrent: 1A → 7A**
+
+![Figure 14. Buck Mode: Charge Current Loop to Adapter Current Loop, VADP = 28V, VBAT = 22V, AdapterCurrentLimit = 5A, ChargeCurrent: 1A → 7A](04-typical-performance-graphs/figure-14.png)
+
+**Figure 15. Boost Mode: Charge Current Loop to Input Voltage Loop, V<sub>ADP</sub> = 5V, V<sub>BAT</sub> = 16V, ChargeCurrent: 0.5A → 2A, InputVoltageLimit = 4.096V**
+
+![Figure 15. Boost Mode: Charge Current Loop to Input Voltage Loop, VADP = 5V, VBAT = 16V, ChargeCurrent: 0.5A → 2A, InputVoltageLimit = 4.096V](04-typical-performance-graphs/figure-15.png)
+
+**Figure 16. OTG Mode Enable, OTG_Debounce = 150ms, V<sub>BAT</sub> = 29.4V, V<sub>OTG</sub> = 20V**
+
+![Figure 16. OTG Mode Enable, OTG_Debounce = 150ms, VBAT = 29.4V, VOTG = 20V](04-typical-performance-graphs/figure-16.png)
+
+**Figure 17. OTG Mode Transients, V<sub>BAT</sub> = 29.4V, V<sub>OTG</sub> = 20V, OTG Load: 0.5A ↔ 3A**
+
+![Figure 17. OTG Mode Transients, VBAT = 29.4V, VOTG = 20V, OTG Load: 0.5A ↔ 3A](04-typical-performance-graphs/figure-17.png)
+
+<!-- page 23 -->
+
+## 4.2 NVDC Charging (with BFET)
+
+**Figure 18. Adapter Insertion, V<sub>ADP</sub>: 0V → 5V, V<sub>BAT</sub> = 18V, ChargeCurrent = 0A**
+
+![Figure 18. Adapter Insertion, VADP: 0V → 5V, VBAT = 18V, ChargeCurrent = 0A](04-typical-performance-graphs/figure-18.png)
+
+**Figure 19. Adapter Insertion, V<sub>ADP</sub>: 0V → 5V, V<sub>BAT</sub> = 18V, ChargeCurrent = 0A (Figure 18 Zoomed In)**
+
+![Figure 19. Adapter Insertion, VADP: 0V → 5V, VBAT = 18V, ChargeCurrent = 0A (Figure 18 Zoomed In)](04-typical-performance-graphs/figure-19.png)
+
+**Figure 20. Adapter Removal, V<sub>ADP</sub>: 28V → 0V, V<sub>BAT</sub> = 18V, SystemLoad = 2A**
+
+![Figure 20. Adapter Removal, VADP: 28V → 0V, VBAT = 18V, SystemLoad = 2A](04-typical-performance-graphs/figure-20.png)
+
+**Figure 21. Adapter Voltage Ramp Up, Boost → Buck-Boost → Buck Operation Mode Transitions**
+
+![Figure 21. Adapter Voltage Ramp Up, Boost → Buck-Boost → Buck Operation Mode Transitions](04-typical-performance-graphs/figure-21.png)
+
+**Figure 22. Adapter Voltage Ramp Down, Buck → Buck-Boost → Boost Operation Mode Transitions**
+
+![Figure 22. Adapter Voltage Ramp Down, Buck → Buck-Boost → Boost Operation Mode Transitions](04-typical-performance-graphs/figure-22.png)
+
+<!-- page 24 -->
+
+**Figure 23. Boost Mode: Output Voltage Loop ↔ Adapter Current Loop, V<sub>ADP</sub> = 5V, MaxSystemVoltage = 21V, V<sub>BAT</sub> = 20.5V, AdapterCurrentLimit = 3A, ChargeCurrent = 0A, SystemLoad: 0.2A ↔ 4A**
+
+![Figure 23. Boost Mode: Output Voltage Loop ↔ Adapter Current Loop, VADP = 5V, MaxSystemVoltage = 21V, VBAT = 20.5V, AdapterCurrentLimit = 3A, ChargeCurrent = 0A, SystemLoad: 0.2A ↔ 4A](04-typical-performance-graphs/figure-23.png)
+
+**Figure 24. Boost Mode: Charge Current Loop ↔ Adapter Current Loop, V<sub>ADP</sub> = 5V, MaxSystemVoltage = 21V, V<sub>BAT</sub> = 16V, AdapterCurrentLimit = 3A, ChargeCurrent = 0.5A, SystemLoad: 0A ↔ 4A**
+
+![Figure 24. Boost Mode: Charge Current Loop ↔ Adapter Current Loop, VADP = 5V, MaxSystemVoltage = 21V, VBAT = 16V, AdapterCurrentLimit = 3A, ChargeCurrent = 0.5A, SystemLoad: 0A ↔ 4A](04-typical-performance-graphs/figure-24.png)
+
+**Figure 25. Buck-Boost Mode: Output Voltage Loop ↔ Adapter Current Loop, V<sub>ADP</sub> = 20V, MaxSystemVoltage = 21V, V<sub>BAT</sub> = 20.5V, AdapterCurrentLimit = 5A, ChargeCurrent = 0A, SystemLoad: 2A ↔ 8A, Buck_Boost_CCM_stretch_period = 2x**
+
+![Figure 25. Buck-Boost Mode: Output Voltage Loop ↔ Adapter Current Loop, VADP = 20V, MaxSystemVoltage = 21V, VBAT = 20.5V, AdapterCurrentLimit = 5A, ChargeCurrent = 0A, SystemLoad: 2A ↔ 8A, Buck_Boost_CCM_stretch_period = 2x](04-typical-performance-graphs/figure-25.png)
+
+**Figure 26. Buck-Boost Mode: Charge Current Loop ↔ Adapter Current Loop, V<sub>ADP</sub> = 20V, MaxSystemVoltage = 21V, V<sub>BAT</sub> = 20V, AdapterCurrentLimit = 5A, ChargeCurrent = 1A, SystemLoad: 2A ↔ 8A, Buck_Boost_CCM_stretch_period = 2x**
+
+![Figure 26. Buck-Boost Mode: Charge Current Loop ↔ Adapter Current Loop, VADP = 20V, MaxSystemVoltage = 21V, VBAT = 20V, AdapterCurrentLimit = 5A, ChargeCurrent = 1A, SystemLoad: 2A ↔ 8A, Buck_Boost_CCM_stretch_period = 2x](04-typical-performance-graphs/figure-26.png)
+
+**Figure 27. Buck Mode: Output Voltage Loop ↔ Adapter Current Loop, V<sub>ADP</sub> = 28V, MaxSystemVoltage = 21V, V<sub>BAT</sub> = 20.5V, AdapterCurrentLimit = 5A, ChargeCurrent = 0A, SystemLoad: 2A ↔ 12A**
+
+![Figure 27. Buck Mode: Output Voltage Loop ↔ Adapter Current Loop, VADP = 28V, MaxSystemVoltage = 21V, VBAT = 20.5V, AdapterCurrentLimit = 5A, ChargeCurrent = 0A, SystemLoad: 2A ↔ 12A](04-typical-performance-graphs/figure-27.png)
+
+**Figure 28. Buck Mode: Charge Current Loop ↔ Adapter Current Loop, V<sub>ADP</sub> = 28V, MaxSystemVoltage = 21V, V<sub>BAT</sub> = 20V, AdapterCurrentLimit = 5A, ChargeCurrent = 1A, SystemLoad: 2A ↔ 12A**
+
+![Figure 28. Buck Mode: Charge Current Loop ↔ Adapter Current Loop, VADP = 28V, MaxSystemVoltage = 21V, VBAT = 20V, AdapterCurrentLimit = 5A, ChargeCurrent = 1A, SystemLoad: 2A ↔ 12A](04-typical-performance-graphs/figure-28.png)
+
+<!-- page 25 -->
+
+**Figure 29. Boost Mode: Output Voltage Loop ↔ Input Voltage Loop, V<sub>ADP</sub> = 5V, MaxSystemVoltage = 21V, V<sub>BAT</sub> = 20.5V, InputVoltageLimit = 4.096V, ChargeCurrent = 0A, SystemLoad: 0A ↔ 4A**
+
+![Figure 29. Boost Mode: Output Voltage Loop ↔ Input Voltage Loop, VADP = 5V, MaxSystemVoltage = 21V, VBAT = 20.5V, InputVoltageLimit = 4.096V, ChargeCurrent = 0A, SystemLoad: 0A ↔ 4A](04-typical-performance-graphs/figure-29.png)
+
+**Figure 30. Boost Mode: Charge Current Loop ↔ Input Voltage Loop, V<sub>ADP</sub> = 5V, MaxSysVoltage = 21V, V<sub>BAT</sub> = 16V, InputVoltageLimit = 4.096V, ChargeCurrent = 0.5A, SystemLoad: 0A ↔ 4A**
+
+![Figure 30. Boost Mode: Charge Current Loop ↔ Input Voltage Loop, VADP = 5V, MaxSysVoltage = 21V, VBAT = 16V, InputVoltageLimit = 4.096V, ChargeCurrent = 0.5A, SystemLoad: 0A ↔ 4A](04-typical-performance-graphs/figure-30.png)
+
+**Figure 31. OTG Mode Enable. OTG_Debounce = 150ms, V<sub>BAT</sub> = 29.4V, V<sub>OTG</sub> = 20V**
+
+![Figure 31. OTG Mode Enable. OTG_Debounce = 150ms, VBAT = 29.4V, VOTG = 20V](04-typical-performance-graphs/figure-31.png)
+
+**Figure 32. OTG Mode Transients. V<sub>BAT</sub> = 29.4V, V<sub>OTG</sub> = 20V, OTG Current = 5A, OTG Load: 0.5A ↔ 3A**
+
+![Figure 32. OTG Mode Transients. VBAT = 29.4V, VOTG = 20V, OTG Current = 5A, OTG Load: 0.5A ↔ 3A](04-typical-performance-graphs/figure-32.png)

REN_RAA489118/05-general-smbus-architecture.md

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+<!-- page 26 -->
+
+# 5. General SMBus Architecture
+
+**Figure 33. General SMBus**
+
+![Figure 33. General SMBus](05-general-smbus-architecture/figure-33.png)
+
+## 5.1 Data Validity
+
+The data on the `SDA` line must be stable during the HIGH period of the `SCL`, unless generating a START or STOP condition. The HIGH or LOW state of the data line can change only when the clock signal on the `SCL` line is LOW. See Figure 34.
+
+**Figure 34. Data Validity**
+
+![Figure 34. Data Validity](05-general-smbus-architecture/figure-34.png)
+
+## 5.2 START and STOP Conditions
+
+In Figure 35, the START condition is a HIGH to LOW transition of the `SDA` line while `SCL` is HIGH.
+
+The STOP condition is a LOW to HIGH transition on the `SDA` line while `SCL` is HIGH. A STOP condition must be sent before each START condition.
+
+<!-- page 27 -->
+
+**Figure 35. Start and Stop Waveforms**
+
+![Figure 35. Start and Stop Waveforms](05-general-smbus-architecture/figure-35.png)
+
+## 5.3 Acknowledge
+
+Each address and data transmission uses nine clock pulses. The ninth pulse is the Acknowledge bit (ACK). After the start condition, the master sends seven slave address bits and a `R/W` bit during the next eight clock pulses. During the ninth clock pulse, the device that recognizes its own address holds the data line LOW to acknowledge (see Figure 36). Both the master and the slave use the ACK bit to acknowledge receipt of register addresses and data.
+
+**Figure 36. Acknowledge On The SMBus**
+
+![Figure 36. Acknowledge On The SMBus](05-general-smbus-architecture/figure-36.png)
+
+## 5.4 SMBus Transactions
+
+All transactions start with a control byte sent from the SMBus master device. The control byte begins with a Start condition followed by seven bits of slave address (0001001) and the `R/W` bit. The `R/W` bit is 0 for a WRITE or 1 for a READ. If any slave device on the SMBus bus recognizes its address, it acknowledges by pulling the Serial Data (`SDA`) line LOW for the last clock cycle in the control byte. If no slave exists at that address or it is not ready to communicate, the data line is 1 indicating a not acknowledge condition.
+
+When the control byte is sent and the RAA489118 acknowledges it, the second byte sent by the master must be a register address byte such as `0x14` for the `ChargeCurrent` register. The register address byte tells the RAA489118 which register the master writes or reads. See Table 1 for register details. When the RAA489118 receives a register address byte, it responds with an acknowledge.
+
+## 5.5 Byte Format
+
+Every byte on the `SDA` line must be eight bits long and must be followed by an ACK bit. Data is transferred with the Most Significant Bit (MSB) first and the Least Significant Bit (LSB) last. The LO Byte data is transferred before the HI Byte data. For example, when writing `0x41A0`, `0xA0` is written first and `0x41` is written second.
+
+<!-- page 28 -->
+
+**Figure 37. SMBus Read and Write Protocol**
+
+![Figure 37. SMBus Read and Write Protocol](05-general-smbus-architecture/figure-37.png)
+
+## 5.6 SMBus and I2C Compatibility
+
+The RAA489118 SMBus minimum input logic high voltage is 1.3V, so it is compatible with I2C with pull-up power supplies higher than 1.3V.
+
+The RAA489118 SMBus registers are 16 bits, so it is compatible with 16-bit I2C or 8-bit I2C with auto-increment capability.
+
+## 5.7 SMBus Commands
+
+The RAA489118 receives control inputs from the SMBus interface after Power-On Reset (POR). The serial interface complies with the System Management Bus Specification. The RAA489118 uses the SMBus Read-word and Write-word protocols (see Figure 37) to communicate with the host system and a smart battery. The RAA489118 is an SMBus slave device and does not initiate communication on the bus. It responds to the 7-bit address `0b0001001_` as follows:
+
+The Read and Write address for the RAA489118 is:
+
+- Read address = `0b00010011` (`0X13H`)
+- Write address = `0b00010010` (`0X12H`)
+
+The data (`SDA`) and clock (`SCL`) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose pull-up resistors for `SDA` and `SCL` to achieve rise times according to the SMBus specifications.

REN_RAA489118/06-registers.md

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+<!-- page 29 -->
+
+# 6. Registers
+
+The register descriptions below are based on current-sensing resistors R<sub>s1</sub> = 10mΩ and R<sub>s2</sub> = 5mΩ, unless otherwise specified.
+
+## 6.1 Register Summary
+
+**Table 1. Register Summary**
+
+| Register Names | Register Address | Read/ Write | Number of Bits | Description | Default |
+| --- | --- | --- | --- | --- | --- |
+| `ChargeCurrentLimit` | `0x14` | R/W | 11 | [12:2], LSB size 8mA | 256mA: `CONFIG` = VDD<br>0A: Otherwise |
+| `MaxSystemVoltage` | `0x15` | R/W | 12 | [14:3], LSB size 16mV | 8.4V<br>12.608V<br>16.8V<br>21.008V<br>25.2V<br>29.408V<br>(Set by `PROG` pin) |
+| `Control7` | `0x36` | R/W | 3 | [7], [1:0], configures various charger options | `0x0000` |
+| `Control6` | `0x37` | R/W | 8 | [7:0], configures various charger options | `0x0040` or `0x0043`[1] |
+| `Control5` | `0x38` | R/W | 16 | Configures various charger options | `0x0000` |
+| `Control0` | `0x39` | R/W | 16 | Configures various charger options | `0x0000` |
+| `Information1` | `0x3A` | R | 16 | Indicates various charger statuses | `0x0000` |
+| `AdapterCurrentLimit2` | `0x3B` | R/W | 11 | [12:2], LSB size 8mA | 1.504A |
+| `Control1` | `0x3C` | R/W | 16 | Configures various charger options | `0x0200` |
+| `Control2` | `0x3D` | R/W | 16 | Configures various charger options | `0x0000` |
+| `MinSystemVoltage` | `0x3E` | R/W | 8 | [13:6], LSB size 128mV | 5.12V<br>7.68V<br>10.24V<br>12.80V<br>15.36V<br>17.92V<br>(Set by `PROG` pin) |
+| `AdapterCurrentLimit1` | `0x3F` | R/W | 11 | [12:2], LSB size 8mA | 0.48A or 1.504A<br>(Set by `PROG` pin) |
+| Revision ID | `0x44` | R | 8 | Revision ID register - Read only | `0x00` |
+| `ACProchot#` | `0x47` | R/W | 6 | [12:7] Adapter current `PROCHOT#` threshold, 256mA resolution for 10mΩ R<sub>s1</sub>. | 3.072A |
+| `DCProchot#` | `0x48` | R/W | 6 | [13:8] Battery discharging current `PROCHOT#` threshold, 512mA resolution for 5mΩ R<sub>s2</sub>. | 4.096A |
+| OTG Voltage | `0x49` | R/W | 12 | [14:3], LSB size 18mV,<br>OTG mode voltage reference | 5.004V |
+| OTG Current | `0x4A` | R/W | 9 | [12:4], LSB size 32mA,<br>OTG mode maximum current limit | 0.512A |
+
+<!-- page 30 -->
+
+**Table 1. Register Summary (Cont.)**
+
+| Register Names | Register Address | Read/ Write | Number of Bits | Description | Default |
+| --- | --- | --- | --- | --- | --- |
+| V<sub>IN</sub> Voltage | `0x4B` | R/W | 6 | [13:8], LSB size 512mV,<br>V<sub>IN</sub> loop voltage reference | 4.096V |
+| `Control3` | `0x4C` | R/W | 16 | Configures various charger options | `0x0000` or `0x0080`[2] |
+| `Information2` | `0x4D` | R | 16 | Indicates various charger statuses | `0x0000` |
+| `Control4` | `0x4E` | R/W | 16 | Configures various charger options | `0x0000` |
+| `Information3` | `0x90` | R | 1 | [1] indicates pass-through mode status | `0x0000` |
+| Manufacturer ID | `0xFE` | R | 8 | Manufacturer ID register – `0x49` - Read only | `0x0049` |
+| Device ID | `0xFF` | R | 8 | Device ID register - Read only | `0x0018` |
+
+1. The default value for the VSYS UV field depends on the `CONFIG` pin state and whether powering up from battery.
+2. `Control3` Bit[7] is set by `PROG` pin, see Table 16.
+
+<!-- page 31 -->
+
+## 6.2 DAC Register Summary
+
+**Table 2. DAC Summary Table[1]**
+
+| ADDR Bit | Charge Current Limit (R<sub>s2</sub> = 5mΩ) | Max System Voltage | Min System Voltage | Adapter Current Limit1 (R<sub>s1</sub> = 10mΩ) | Adapter Current Limit2 (R<sub>s1</sub> = 10mΩ) | V<sub>IN</sub> Voltage (ADP Min Voltage or BAT Min Voltage) | ACProchot# (ACHOT) (R<sub>s1</sub> = 10mΩ) | DCProchot# (DCHOT) (R<sub>s2</sub> = 5mΩ) | OTG Voltage | OTG Current (R<sub>s1</sub> = 10mΩ) |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+|  | `0x14` | `0x15` | `0x3E` | `0x3F` | `0x3B` | `0x4B` | `0x47` | `0x48` | `0x49` | `0x4A` |
+| `[0]` | - | - | - | - | - | - | - | - | - | - |
+| `[1]` | - | - | - | - | - | - | - | - | - | - |
+| `[2]` | 8mA | - | - | 8mA | 8mA | - | - | - | - | - |
+| `[3]` | 16mA | 16mV | - | 16mA | 16mA | - | - | - | 18mV | - |
+| `[4]` | 32mA | 32mV | - | 32mA | 32mA | - | - | - | 36mV | 32mA |
+| `[5]` | 64mA | 64mV | - | 64mA | 64mA | - | - | - | 72mV | 64mA |
+| `[6]` | 128mA | 128mV | 128mV | 128mA | 128mA | - | - | - | 144mV | 128mA |
+| `[7]` | 256mA | 256mV | 256mV | 256mA | 256mA | - | 256mA | - | 288mV | 256mA |
+| `[8]` | 512mA | 512mV | 512mV | 512mA | 512mA | 512mV | 512mA | 512mA | 576mV | 512mA |
+| `[9]` | 1024mA | 1024mV | 1024mV | 1024mA | 1024mA | 1024mV | 1024mA | 1024mA | 1152mV | 1024mA |
+| `[10]` | 2048mA | 2048mV | 2048mV | 2048mA | 2048mA | 2048mV | 2048mA | 2048mA | 2304mV | 2048mA |
+| `[11]` | 4096mA | 4096mV | 4096mV | 4096mA | 4096mA | 4096mV | 4096mA | 4096mA | 4608mV | 4096mA |
+| `[12]` | 8192mA | 8192mV | 8192mV | 8192mA | 8192mA | 8192mV | 8192mA | 8192mA | 9216mV | 8192mA |
+| `[13]` | - | 16384mV | 16384mV | - | - | 16384mV | - | 16384mA | 18432mV | - |
+| `[14]` | - | 0mV | - | - | - | - | - | - | 0mV | - |
+| `[15]` | - | - | - | - | - | - | - | - | - | - |
+| Max | 12.16A (`0x17C0`) | 32.256V (`0x3F00`) | 25.088V (`0x3100`) | 12.16A (`0x17C0`) | 12.16A (`0x17C0`) | 27.648A (`0x3600`) | 12.8A (`0x1900`) | 25.6A (`0x3200`) | 32.256V (`0x3800`) | 8.192A (`0x1000`) |
+| Default | CFG = VDD: 0.256A (`0x0080`)<br>CFG ≠ VDD: 0A (`0x0000`) | Set by `PROG` | Set by `PROG` | 0.48A (`0x00F0`) or 1.504A (`0x02F0`) (Set by `PROG`) | 1.504A (`0x02F0`) | 4.096V (`0x0800`) | 3.072A (`0x0600`) | 4.096A (`0x0800`) | 5.004V (`0x08B0`) | 0.512A (`0x0100`) |
+
+1. Each of the DAC registers accepts any value, but only the valid register bits are written to the register and the voltage or current value is clamped at the indicated maximum. The RAA489118 accepts a 0V command for the `MaxSystemVoltage` register, but the register value does not change. The `MinSystemVoltage` value should be lower than the `MaxSystemVoltage` value.
+
+<!-- page 32 -->
+
+## 6.3 Control Registers
+
+The Control registers configure the operation of the RAA489118. To change the configuration after a POR, write to the appropriate control registers using the Write-word protocol shown in Figure 37.
+
+**Table 3. Control0 Register 0x39H**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[15:13]` | Forward Buck Phase Comparator Threshold Offset | Bit[15:13] adjusts the phase comparator threshold offset for the forward buck mode.<br>`000` = 0mV (default)<br>`001` = 1mV<br>`010` = 2mV<br>`011` = 3mV<br>`100` = -4mV<br>`101` = -3mV<br>`110` = -2mV<br>`111` = -1mV |
+| `[12:10]` | Forward Buck-boost, Forward Boost, and Reverse Boost Phase Comparator Threshold Offset | Bit[12:10] adjusts the phase comparator threshold offset for the forward buck-boost, forward boost, and reverse boost modes.<br>`000` = 0mV (default)<br>`001` = 0.5mV<br>`010` = 1mV<br>`011` = 1.5mV<br>`100` = -2mV<br>`101` = -1.5mV<br>`110` = -1mV<br>`111` = -0.5mV |
+| `[9,8,0]` | Reverse Buck and Reverse Buck-boost Phase Comparator Threshold Offset | Bit[9,8,0] adjusts the phase comparator threshold offset for the reverse buck and reverse buck-boost modes.<br>`000` = 0mV (default)<br>`001` = 1mV<br>`010` = 2mV<br>`011` = 3mV<br>`100` = -4mV<br>`101` = -3mV<br>`110` = -2mV<br>`111` = -1mV |
+| `[7]` | SMBus Timeout | Bit[7] enables or disables the charger timeout function in NVDC charging mode (`CONFIG` pulled low). If the adapter is present and the RAA489118 does not receive a write command to the `MaxSystemVoltage`(`0x15`) or `ChargeCurrentLimit`(`0x14`) register within the time set by `Control3` register Bit[12:11], RAA489118 terminates charging. After the timeout occurs, writing the `MaxSystemVoltage`(`0x15`) or `ChargeCurrentLimit`(`0x14`) register re-enables charging.<br>`0` = Enable the SMBus timeout function (default)<br>`1` = Disable the SMBus timeout function<br>For battery-charging only mode (`CONFIG` tied to VDD), this bit is irrelevant and the SMBus Timeout feature is always disabled. |
+| `[6:5]` | High-Side FET Short Detection Threshold | Bit[6:5] configures the high-side FET short detection phase node voltage threshold while the low-side FET turns on.<br>`00` = 800mV (default)<br>`01` = 500mV<br>`10` = 600mV<br>`11` = 400mV |
+
+<!-- page 33 -->
+
+**Table 3. Control0 Register 0x39H (Cont.)**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[4:3]` | DCProchot# Threshold in Battery Only Low Power Mode | `Control7`[1] and `Control0`[4:3] configure the battery discharging current `DCProchot#` threshold in battery only Low Power mode as indicated by `Information1` register `0x3A` Bit[15]. If PSYS is enabled, the battery discharge current `DCProchot#` threshold is instead set by the `DCProchot#` register `0x48` setting.<br><table><thead><tr><th>Control7[1]</th><th>Control0[4:3]</th><th>R<sub>s2</sub> = 20mΩ (A)</th><th>R<sub>s2</sub> = 10mΩ (A)</th><th>R<sub>s2</sub> = 5mΩ (A)</th></tr></thead><tbody><tr><td>0 (default)</td><td>00 (default)</td><td>6</td><td>12</td><td>24</td></tr><tr><td>0</td><td>01</td><td>5</td><td>10</td><td>20</td></tr><tr><td>0</td><td>10</td><td>4</td><td>8</td><td>16</td></tr><tr><td>0</td><td>11</td><td>3</td><td>6</td><td>12</td></tr><tr><td>1</td><td>00</td><td>2.5</td><td>5</td><td>10</td></tr><tr><td>1</td><td>01</td><td>2</td><td>4</td><td>8</td></tr><tr><td>1</td><td>10</td><td>1.5</td><td>3</td><td>6</td></tr><tr><td>1</td><td>11</td><td>1</td><td>2</td><td>4</td></tr></tbody></table> |
+| `[2]` | Input Voltage Regulation Loop | Bit[2] enables or disables the input voltage regulation loop.<br>`0` = Enable the input voltage regulation loop (default)<br>`1` = Disable the input voltage regulation loop |
+| `[1]` | Force Buck Mode | Bit[1] disables or enables Force Buck mode. If the Force Buck mode bit is enabled, the Buck-Boost window narrows.<br>`0` = Disable Force Buck mode (default)<br>`1` = Enable Force Buck mode |
+
+**Table 4. Control1 Register 0x3CH**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[15:14]` | General Purpose Comparator Assertion Debounce Time | Bit[15:14] configures the general purpose comparator assertion debounce time.<br>`00` = 2µs (default)<br>`01` = 12µs<br>`10` = 2ms<br>`11` = 5s |
+| `[13]` | Exit Learn Mode Option | Bit[13] provides the option to Exit Learn mode when the battery voltage is lower than the `MinSystemVoltage` register setting.<br>`0` = Stay in Learn mode even if V<sub>BAT</sub> < `MinSystemVoltage` register setting (default)<br>`1` = Exit Learn mode if V<sub>BAT</sub> < `MinSystemVoltage` register setting |
+| `[12]` | Learn Mode | Bit[12] enables or disables Battery Learn mode.<br>`0` = Disable Battery Learn mode (default)<br>`1` = Enable Battery Learn mode<br>To enter Learn mode, the `BATGONE` pin must be low, that is, the battery must be present. Renesas recommends to disable the slew rate control (`Control6` Bit[6] = `0`) when using Learn mode. |
+| `[11]` | OTG Function | Bit[11] enables or disables the OTG function.<br>`0` = Disable the OTG function (default)<br>`1` = Enable the OTG function |
+
+<!-- page 34 -->
+
+**Table 4. Control1 Register 0x3CH (Cont.)**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[10]` | Audio Filter | Bit[10] enables or disables the audio filter function.<br>`0` = Disable the audio filter function (default)<br>`1` = Enable the audio filter function |
+| `[9:8]` | Switching Frequency | Bit[9:8] configures the switching frequency.<br>`00` = 1MHz<br>`01` = 839kHz<br>`10` = 732kHz (default)<br>`11` = 635kHz |
+| `[7]` | Not Used | Not used |
+| `[6]` | Turbo | Bit[6] enables or disables Turbo mode. When the turbo function is enabled, the `BGATE` FET turns on in Turbo mode. See Table 15 for the `BGATE` ON/OFF truth table.<br>`0` = Enable Turbo mode (default)<br>`1` = Disable Turbo mode |
+| `[5]` | AMON/BMON Function | Bit[5] enables or disables the current monitor function AMON and BMON.<br>`0` = Enable AMON/BMON (default)<br>`1` = Disable AMON/BMON<br>Bit[5] is only valid in Battery Only mode. When the adapter is present, AMON/BMON is automatically enabled and Bit[5] becomes invalid. |
+| `[4]` | AMON or BMON | Bit[4] selects AMON or BMON as the `AMON/BMON` pin output.<br>`0` = AMON (default)<br>`1` = BMON |
+| `[3]` | PSYS | Bit[3] enables or disables the system power monitor PSYS function.<br>`0` = Disables the PSYS function (default)<br>`1` = Enables the PSYS function |
+| `[2]` | VSYS | Bit[2] enables or disables the buck-boost charger switching VSYS output. When disabled, the RAA489118 stops switching and forces the `BGATE` FET on.<br>`0` = Enables VSYS output (default)<br>`1` = Disables VSYS output |
+| `[1:0]` | Low_VSYS_Prochot# Reference | Bit[1:0] configures the `Low_VSYS_Prochot#` assertion.<br>`00` = 6.0V (default)<br>`01` = 6.3V<br>`10` = 6.6V<br>`11` = 6.9V |
+
+<!-- page 35 -->
+
+**Table 5. Control2 Register 0x3DH**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[15:14]` | Trickle Charging Current | Bit[15:14] configures the charging current in Trickle Charging mode.<br>`00` = 512mA (default)<br>`01` = 256mA<br>`10` = 128mA<br>`11` = 1024mA |
+| `[13]` | OTG Function Enable Debounce Time | Control2 Bit[13] and Control 3 Bit[0] configures the OTG function debounce time from when the RAA489118 receives the OTG enable command.<br><table><thead><tr><th>Control2[13]</th><th>Control3[0]</th><th>OTG Start-Up Delay</th></tr></thead><tbody><tr><td>0 (default)</td><td>0 (default)</td><td>1.3s</td></tr><tr><td>0</td><td>1</td><td>1.3s</td></tr><tr><td>1</td><td>0</td><td>150ms</td></tr><tr><td>1</td><td>1</td><td>7.5ms</td></tr></tbody></table> |
+| `[12]` | Two-Level Adapter Current Limit Function | Bit[12] enables or disables the two-level adapter current limit function.<br>`0` = Disables the two-level current limit function (default)<br>`1` = Enables the two-level current limit function |
+| `[11]` | Adapter Insertion to Switching Debounce | Bit[11] configures the debounce time from adapter insertion to when `ACOK` is asserted high.<br>`0` = 1.3s (default)<br>`1` = 150ms<br>After VDD POR, for the first time the adapter is plugged in, the ASGATE turn-on delay is always 150ms, regardless of the Bit[11] setting. This bit sets the ASGATE turn-on delay only after ASGATE turns off at least one time when VDD is above its POR value and the Bit[11] default is 0 for 1.3s. |
+| `[10:9]` | Prochot# Debounce | Bit[10:9] configures the `PROCHOT#` debounce time before its assertion for ACProchot# and DCProchot#. The Low_VSYS_Prochot# has a fixed 8µs debounce time.<br>`00`: 7µs (default)<br>`01`: 100µs<br>`10`: 500µs<br>`11`: 1ms |
+| `[8:6]` | Prochot# Duration | Bit[8:6] configures the minimum duration of the `PROCHOT#` signal when asserted.<br>`000` = 10ms (default)<br>`001` = 20ms<br>`010` = 15ms<br>`011` = 5ms<br>`100` = 1ms<br>`101` = 500µs<br>`110` = 100µs<br>`111` = 0s |
+| `[5]` | ASGATE in OTG Mode | Bit[5] turns the ASGATE FET on or off in OTG mode.<br>`0` = Turn on ASGATE in OTG mode (default)<br>`1` = Turn off ASGATE in OTG mode |
+
+<!-- page 36 -->
+
+**Table 5. Control2 Register 0x3DH  (Cont.)**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[4]` | CMIN Reference | Bit[4] configures the general purpose comparator reference voltage when an adapter is attached. (In Battery-Only low-power mode, the reference voltage is 1.2V regardless of this bit.)<br>`0` = 1.2V (default)<br>`1` = 2V |
+| `[3]` | General Purpose Comparator | Bit[3] enables or disables the general purpose comparator.<br>`0` = Enable the general purpose comparator (default)<br>`1` = Disable the general purpose comparator |
+| `[2]` | CMOUT Polarity | Bit[2] configures the general purpose comparator output polarity when asserted. The comparator reference voltage is connected at the inverting input node.<br>`0` = `CMOUT` is High when `CMIN` is higher than reference (default)<br>`1` = `CMOUT` is Low when `CMIN` is higher than reference |
+| `[1:0]` | Pass-Through Mode | Bit[1:0] configures the Pass-Through Mode (PTM).<br>`00` = Disable normal PTM and forced PTM (default)<br>`01` = Enable normal PTM<br>`10` = Not Used<br>`11` = Enable Forced PTM |
+
+**Table 6. Control3 Register 0x4CH**
+
+| Bit | Bit Name | Description<sup>7</sup> |
+| --- | --- | --- |
+| `[15]` | Reread PROG Pin Resistor | Bit[15] specifies whether to reread the `PROG` pin resistor.<br>`0` = Reread `PROG` pin resistor (default)<br>`1` = Do not reread `PROG` pin resistor |
+| `[14]` | Reload ACLIM When Adapter Is Plugged In | Bit[14] specifies whether to reload the `AdapterCurrentLimit1` register set by the `PROG` pin resistor.<br>`0` = Reload the `AdapterCurrentLimit1` register (default)<br>`1` = Do not reload the `AdapterCurrentLimit1` register |
+| `[13]` | Autonomous Charging Termination Time | Bit[13] configures the autonomous charging termination time.<br>`0` = 20ms (default)<br>`1` = 200ms |
+| `[12:11]` | Charger Timeout | Bit[12:11] configures the SMBus charger timeout time.<br>`00` = 175s (default)<br>`01` = 87.5s<br>`10` = 43.75s<br>`11` = 5s |
+| `[10]` | BGATE Force OFF | Bit[10] configures the BGATE operation between normal and force off.<br>`0` = Normal BGATE operation (default)<br>`1` = Force BGATE MOSFET off |
+| `[9]` | PSYS Gain | Bit[9] configures the system power monitor `PSYS` output gain.<br>`0` = 0.236µA/W (default)<br>`1` = 0.118µA/W |
+
+<!-- page 37 -->
+
+**Table 6. Control3 Register 0x4CH (Cont.)**
+
+| Bit | Bit Name | Description<sup>7</sup> |
+| --- | --- | --- |
+| `[8]` | Exit IDM Timer | Control7[7] and Control3[8] configure the Ideal Diode mode exit timer when the battery discharge current is less than 380mA.<br><table><thead><tr><th>Control3 [8]</th><th>Control7 [7]</th><th>IDM Timer</th></tr></thead><tbody><tr><td>0 (default)</td><td>0 (default)</td><td>40ms</td></tr><tr><td>0</td><td>1</td><td>5ms</td></tr><tr><td>1</td><td>0</td><td>80ms</td></tr><tr><td>1</td><td>1</td><td>1ms</td></tr></tbody></table> |
+| `[7]` | Charging Mode | Bit[7] selects the charging mode.<br>`0` = Enable Autonomous Charging mode<br>`1` = Battery charging current control through SMBus<br>Default is determined by `PROG` and `CONFIG`. |
+| `[6]` | AC and CC Feedback Gain | Bit[6] configures AC and CC feedback gain for high current.<br>`0` = x1 (default)<br>`1` = x0.5 |
+| `[5]` | Adapter-Side Current Limit Loop | Bit[5] enables or disables the adapter-side input current limit loops for forward and reverse/OTG modes.<br>`0` = Enable adapter-side current limit loops (default)<br>`1` = Disable adapter-side current limit loops |
+| `[4]` | Adapter-Side Current Limit Loop when BATGONE = 1 | Bit[4] enables or disables the adapter-side current limit loop, in forward mode, when `BATGONE` = 1.<br>`0` = Enable adapter-side current limit loop when `BATGONE` = 1 (default)<br>`1` = Disable adapter-side current limit loop when `BATGONE` = 1 |
+| `[3]` | AMON/BMON Direction | Bit[3] configures the `AMON`/`BMON` direction.<br>`0` = Adapter current monitor/battery charging current monitor (default)<br>`1` = OTG output current monitor/battery discharging current monitor |
+| `[2]` | Digital Reset | Bit[2] resets all SMBus register values to the POR default value.<br>`0` = Idle (default)<br>`1` = Reset |
+| `[1]` | Buck-Boost Stretch CCM Period | Control3 Bit[1] and Control4 Bit[8] configure the Buck-Boost stretch CCM period (T2 TIME).<br><table><thead><tr><th>Control3[1]</th><th>Control4[8]</th><th>T2 Time</th></tr></thead><tbody><tr><td>0</td><td>0</td><td>0.6x (default)</td></tr><tr><td>0</td><td>1</td><td>1x</td></tr><tr><td>1</td><td>0</td><td>3x</td></tr><tr><td>1</td><td>1</td><td>2x</td></tr></tbody></table> |
+| `[0]` | OTG Start-Up Delay | Refer to the description of Control2[13] in Table 5. |
+
+<!-- page 38 -->
+
+**Table 7. Control4 Register 0x4EH**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[15:14]` | Dither Enable | Bit[15:14] disables or selects the switching frequency dithering function.<br>`00` = Disable dither (default)<br>`01` = Dither 100 - 102%<br>`10` = Dither 100 - 104%<br>`11` = Dither 100 - 106% |
+| `[13]` | ADP Discharge | Bit[13] enables or disables the ADP discharge function. Typical 10mA.<br>`0` = Disable ADP discharge function (default)<br>`1` = Enable ADP discharge function |
+| `[12]` | VSYS Sink | Bit[12] enables or disables the `VSYS` discharge function. Typical 10mA.<br>`0` = Disable `VSYS` discharge function (default)<br>`1` = Enable `VSYS` discharge function |
+| `[11]` | BGATE Tri-state | Bit[11] enables or disables the BGATE tri-state function.<br>`0` = Disable BGATE tri-state (default)<br>`1` = Enable BGATE tri-state |
+| `[10]` | Buck-Boost Min T3 Time | Bit[10] selects the minimum T3 time when in the buck-boost mode.<br>`0` = Long (default)<br>`1` = Short |
+| `[9]` | Buck-Boost T2 time in DCM | Bit[9] selects the buck-boost T2 time in the discontinuous-conduction mode (DCM).<br>`0` = Reduced T2 time (increases switching frequency in DCM) (default)<br>`1` = Normal T2 time |
+| `[8]` | Buck-Boost Stretch CCM Period | Refer to the description of Control3 Bit[1] in Table 6. |
+| `[7]` | OTGCURRENT PROCHOT# | Bit[7] enables or disables `PROCHOT#` trigger with `OTGCURRENT`.<br>`0` = Disable `PROCHOT#` trigger with `OTGCURRENT` (default)<br>`1` = Enable `PROCHOT#` trigger with `OTGCURRENT` |
+| `[6]` | BATGONE PROCHOT# | Bit[6] enables or disables `PROCHOT#` trigger with `BATGONE`.<br>`0` = Disable `PROCHOT#` trigger with `BATGONE` (default)<br>`1` = Enable `PROCHOT#` trigger with `BATGONE` |
+| `[5]` | ACOK PROCHOT# | Bit[5] enables or disables `PROCHOT#` trigger with `ACOK`.<br>`0` = Disable `PROCHOT#` trigger with `ACOK` (default)<br>`1` = Enable `PROCHOT#` trigger with `ACOK` |
+| `[4]` | Comparator PROCHOT# | Bit[4] enables or disables `PROCHOT#` trigger with General Purpose Comparator rising.<br>`0` = Disable `PROCHOT#` trigger with General Purpose Comparator rising (default)<br>`1` = Enable `PROCHOT#` trigger with General Purpose Comparator rising |
+| `[3:2]` | ACOK falling or BATGONE Rising Debounce | Bit[3:2] configures the debounce time from `ACOK` falling or `BATGONE` rising to `PROCHOT#` trip.<br>`00` = 2µs (default)<br>`01` = 25µs<br>`10` = 125µs<br>`11` = 250µs |
+
+<!-- page 39 -->
+
+**Table 7. Control4 Register 0x4EH (Cont.)**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[1]` | PROCHOT# Clear | Bit[1] clears `PROCHOT#`.<br>`0` = Idle (default)<br>`1` = Clear `PROCHOT#` |
+| `[0]` | PROCHOT# Latch | Bit[0] manually resets `PROCHOT#`.<br>`0` = `PROCHOT#` signal auto-clear (default)<br>`1` = Latch `PROCHOT#` low when tripped |
+
+**Table 8. Control5 Register 0x38H**
+
+| Bit | Bit Name | Descriptions |
+| --- | --- | --- |
+| `[15:14]` | Internal Compensation Resistance | Bit[15:14] set the internal compensation resistance<br>`00` = 1.26 KΩ (default)<br>`01` = 773Ω<br>`10` = 3.6 KΩ<br>`11` = 1.88 KΩ |
+| `[13]` | Force BGATE On | Bit[13] enables or disables the Force BGATE On function<br>`0` = Normal BGATE operation (default)<br>`1` = Force BGATE On |
+| `[12]` | Unused | - |
+| `[11]` | VBAT Regulation Loop in OTG Mode | Bit[11] enables or disables the VBAT (VIN) voltage regulation during OTG (reverse) mode<br>`0` = Disable (default)<br>`1` = Enable |
+| `[10:8]` | Two-Level ACLIM T2 Time | Bit[10:8] sets the T2 time corresponding to `AdapterCurrentLimit2` when two-level adapter current limit function is enabled.<br>`000` = 10µs (default)<br>`001` = 100µs<br>`010` = 500µs<br>`011` = 1ms<br>`100` = 300µs<br>`101` = 750µs<br>`110` = 2ms<br>`111` = 10ms |
+| `[7]` | VSYSOK 0.6V Comparator | Bit[7] enables or disables the 0.6V comparator.<br>`0` = Enable (default)<br>`1` = Disable |
+| `[6]` | VSYSOK 10mA Current Source | Bit[6] enables or disables the 10mA current source.<br>`0` = Enable (default)<br>`1` = Disable |
+| `[5]` | OTGPG/CMOUT Selection | Bit[5] selects the signal routed to the `OTGPG`/`CMOUT` pin.<br>`0` = `OTGPG` (default)<br>`1` = `CMOUT` |
+| `[4]` | VSYSOV/OTGOV Control | Bit[4] enables or disables `VSYS` and OTG overvoltage protections.<br>`0` = Enable (default)<br>`1` = Disable |
+
+<!-- page 40 -->
+
+**Table 8. Control5 Register 0x38H**
+
+| Bit | Bit Name | Descriptions |
+| --- | --- | --- |
+| `[3]` | Unused | - |
+| `[2:0]` | Two-Level ACLIM T1 Time | Bit[2:0] sets the T1 time corresponding to `AdapterCurrentLimit1` when two-level adapter current limit function is enabled.<br>`000` = 10ms (default)<br>`001` = 20ms<br>`010` = 15ms<br>`011` = 5ms<br>`100` = 1ms<br>`101` = 0.5ms<br>`110` = 0.1ms<br>`111` = 0ms |
+
+**Table 9. Control6 Register 0x37H**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[15:8]` | Not Used | Not used |
+| `[7]` | Turn off BGATE at VSYSOV | Bit[7] configures the BGATE behavior during `VSYS` overvoltage.<br>`0` = No action (default)<br>`1` = Turn off BGATE |
+| `[6]` | Slew Rate Control for Charge Current, Maximum System Voltage, and OTG Voltage | Bit[6] enables or disables the slew rate control for charger current, maximum system voltage, and OTG voltage.<br>`0` = Disable the slew rate control<br>`1` = Enable the slew rate control (default)<br>Slew is limited to 1 DAC LSB per 16 clock cycles (1µs each). Nominal slew rates: 1mV/µs for system voltage, 0.5mA/µs for charging current with R<sub>s2</sub> = 5mΩ, and 1.125mV/µs for OTG voltage. |
+| `[5]` | OTG Undervoltage Protection | Bit[5] enables or disables the OTG undervoltage protection<br>`0` = Enable OTG undervoltage protection (default)<br>`1` = Disable OTG undervoltage protection |
+| `[4]` | Clear CMOUT Latch Data | Bit[4] clears the current `CMOUT` data when written to 1. The `CMOUT` latch data can be read from Bit[4] when Control6[3] = 0 (`CMOUT` Latch is enabled).<br>`0` = Do not clear `CMOUT` latch data (default)<br>`1` = Clear `CMOUT` latch data |
+| `[3]` | CMOUT Latch | Bit[3] enables or disables the `CMOUT` latch function.<br>`0` = Enable the `CMOUT` latch function (default)<br>`1` = Disable the `CMOUT` latch function |
+| `[2:0]` | VSYS Undervoltage Threshold | Bit[2:0] set `VSYS` under voltage threshold.<br>`000` = Disable (default when `CONFIG` = VDD or when inserting the battery for the first time)<br>`001` = 3.0V<br>`010` = 3.9V<br>`011` = 4.8V (default when `CONFIG` pulled low, except after inserting battery for the first time)<br>`100` = 5.7V<br>`101` = 6.6V<br>`110` = 7.5V<br>`111` = 8.4V |
+
+<!-- page 41 -->
+
+**Table 10. Control7 Register 0x36H**
+
+| Bit | Bit Name | Description |
+| --- | --- | --- |
+| `[15:8]` | Not Used | Not Used |
+| `[7]` | Exit IDM Timer | `Control7[7]` and `Control3[8]` configure the Ideal Diode mode exit timer when the battery discharge current is less than 380mA.<br><table><thead><tr><th>Control3[8]</th><th>Control7[7]</th><th>IDM Timer</th></tr></thead><tbody><tr><td>0 (default)</td><td>0 (default)</td><td>40ms (default)</td></tr><tr><td>0</td><td>1</td><td>5ms</td></tr><tr><td>1</td><td>0</td><td>80ms</td></tr><tr><td>1</td><td>1</td><td>1ms</td></tr></tbody></table> |
+| `[6:2]` | Not Used | Not Used |
+| `[1]` | Battery Only DCProchot# Threshold | Refer to the description of `Control0[4:3]` in Table 3. |
+| `[0]` | VSYS ABS OV | VSYS absolute overvoltage protection<br>`0` = Enabled (default)<br>`1` = Disabled |
+
+## 6.4 Information Registers
+
+The Information registers contain SMBus readable information about manufacturing and Operating modes. The following tables identify the bit locations of the available information.
+
+**Table 11. Information1 Register 0x3AH**
+
+| Bit | Description |
+| --- | --- |
+| `[3:0]` | Not used |
+| `[4]` | `Bit[4]` indicates whether the Trickle Charging mode is active.<br>`0` = Trickle Charging mode is not active<br>`1` = Trickle Charging mode is active |
+| `[9:5]` | Not used |
+| `[10]` | `Bit[10]` indicates whether the `Low_VSYS_Prochot#` is tripped.<br>`0` = `Low_VSYS_Prochot#` is not tripped<br>`1` = `Low_VSYS_Prochot#` is tripped |
+| `[11]` | `Bit[11]` indicates whether `DCProchot#` is tripped.<br>`0` = `DCProchot#` is not tripped<br>`1` = `DCProchot#` is tripped |
+| `[12]` | `Bit[12]` indicates whether `ACProchot#`/`OTGCURRENTProchot#` is tripped.<br>`0` = `ACProchot#`/`OTGCURRENTProchot#` is not tripped<br>`1` = `ACProchot#`/`OTGCURRENTProchot#` is tripped |
+
+<!-- page 42 -->
+
+**Table 11. Information1 Register 0x3AH (Cont.)**
+
+| Bit | Description |
+| --- | --- |
+| `[14:13]` | `Bit[14:13]` indicates the active control loop.<br>`00` = MaxSystemVoltage control loop is active<br>`01` = Charging current loop is active<br>`10` = Adapter current limit loop is active<br>`11` = Input voltage loop is active |
+| `[15]` | `Bit[15]` indicates whether the internal reference circuit is active. `Bit[15]` = 0 indicates that the RAA489118 is in Low Power mode.<br>`0` = Reference is not active<br>`1` = Reference is active |
+
+**Table 12. Information2 Register 0x4DH**
+
+| Bit | Description |
+| --- | --- |
+| `[4:0]` | Program Resister read out<br>MaximumSystemVoltage<br>MinimumSystemVoltage<br>Adapter current limit |
+| `[7:5]` | `Bit[7:5]` indicates the RAA489118 operation mode.<br>`001` = Boost Mode<br>`010` = Buck Mode<br>`011` = Buck-Boost Mode<br>`101` = OTG Boost Mode<br>`110` = OTG Buck Mode<br>`111` = OTG Buck-Boost Mode |
+| `[11:8]` | `Bit[11:8]` indicates the RAA489118 state machine status.<br>`0000` = OFF<br>`0001` = BATTERY<br>`0010` = ADAPTER<br>`0011` = ACOK<br>`0100` = VSYS<br>`0101` = CHARGE<br>`0110` = ENOTG<br>`0111` = OTG<br>`1000` = ENLDO5<br>`1001` = Not Applicable<br>`1010` = TRIM/ENCHREF<br>`1011` = ACHRG<br>`1100` = CAL<br>`1101` = AGON/AGONTG<br>`1110` = WAIT/PSYS<br>`1111` = ADPPSYS |
+| `[12]` | `Bit[12]` indicates the `BATGONE` pin status.<br>`0` = Battery is present (`BATGONE` low)<br>`1` = No battery (`BATGONE` high) |
+| `[13]` | `Bit[13]` indicates the general purpose comparator output after debounce time.<br>`0` = Comparator output is low<br>`1` = Comparator output is high |
+
+<!-- page 43 -->
+
+**Table 12. Information2 Register 0x4DH (Cont.)**
+
+| Bit | Description |
+| --- | --- |
+| `[14]` | `Bit[14]` indicates the `ACOK` pin status.<br>`0` = No adapter<br>`1` = Adapter is present |
+| `[15]` | `Bit[15]` indicates the `CONFIG/PSYS` state.<br>`0` = `CONFIG/PSYS` pulled low (NVDC Charging with BFET)<br>`1` = `CONFIG/PSYS` tied to `VDD` (Battery charging only with no BFET) |
+
+**Table 13. Information3 Register 0x90H**
+
+| Bit | Description |
+| --- | --- |
+| `[15:2]` | Not used |
+| `[1]` | `Bit[1]` indicates the Pass-Through Mode (PTM) status.<br>`0` = PTM is inactive<br>`1` = PTM is active |
+| `[0]` | Not used |

REN_RAA489118/07-modulator-information.md

@@ -0,0 +1,223 @@
+<!-- page 44 -->
+
+# 7. Modulator Information
+
+## 7.1 RAA489118 Buck-Boost Charger Modes of Operation
+
+The RAA489118 buck-boost charger drives an external N-channel MOSFET bridge made of two transistor pairs as shown in Figure 38. The first pair, Q1 and Q2, is a buck arrangement with the transistor center tap connected to an inductor input as is the case with a buck converter. The second transistor pair, Q3 and Q4, is a boost arrangement with the transistor center tap connected to the output of the inductor as is the case with a boost converter. This arrangement supports bucking from a voltage input higher than the battery and also boosting from a voltage input lower than the battery.
+
+**Table 14. Operation Mode**
+
+| Mode | Q1 | Q2 | Q3 | Q4 |
+| --- | --- | --- | --- | --- |
+| Buck | Control FET | Sync. FET | OFF | ON |
+| Boost | ON | OFF | Control FET | Sync. FET |
+| Buck-Boost | Control FET | Sync. FET | Control FET | Sync. FET |
+| OTG Buck | ON | OFF | Sync. FET | Control FET |
+| OTG Boost | Sync. FET | Control FET | OFF | ON |
+| OTG Buck-Boost | Sync. FET | Control FET | Sync. FET | Control FET |
+| Pass-Through | ON | OFF | OFF | ON |
+
+**Figure 38. Buck-Boost Charger Topology**
+
+![Figure 38. Buck-Boost Charger Topology](07-modulator-information/figure-38.png)
+
+The RAA489118 optimizes the Operation mode transition algorithm by comparing the input and output voltage ratio and the load condition. When the adapter voltage V<sub>ADP</sub> is rising and is higher than 91% of the system bus voltage VSYS, the RAA489118 transitions from Boost mode to Buck-Boost mode. If V<sub>ADP</sub> is higher than 114% of VSYS, the RAA489118 forcedly transitions from Buck-Boost mode to Buck mode. At heavier loads, the mode transition point changes accordingly to accommodate the duty cycle change due to the power loss on the charger circuit.
+
+When the adapter voltage V<sub>ADP</sub> is falling and is lower than 108% of the system bus voltage VSYS, the RAA489118 transitions from Buck mode to Buck-Boost mode. If V<sub>ADP</sub> is lower than 85% of VSYS, the RAA489118 transitions from Buck-Boost mode to Boost mode.
+
+<!-- page 45 -->
+
+**Figure 39. Operation Mode**
+
+![Figure 39. Operation Mode](07-modulator-information/figure-39.png)
+
+When the Force Buck Mode is enabled by setting the Control0 Bit[1] to 1, the RAA489118 operates in Buck mode instead of Buck-Boost mode when VADP is 480mV higher than VSYS. Force Buck mode has a 240mV hysteresis window, so the RAA489118 operates in Buck-Boost mode when VADP is lower than VSYS + 240mV.
+
+## 7.2 USB On-the-Go (USB OTG)
+
+When the On-the-Go (OTG) function is enabled with the SMBus command and OTGEN pin, and if the battery voltage V<sub>BAT</sub> is higher than 4.5V, the RAA489118 operates in OTG mode and Control2 Bit[5] controls ASGATE. BATGONE must be low to enable OTG mode.
+
+When the OTG function is enabled with the SMBus command and OTGEN pin and if the battery voltage V<sub>BAT</sub> is higher than 4.5V, the RAA489118 operates in Reverse Buck, Reverse Boost, or Reverse Buck-Boost mode.
+
+When the RAA489118 receives the command to enable the OTG function, it starts switching after the debounce time set by Control2 register Bit[13] and Control3 register Bit[0]. When the OTG output voltage reaches the OTG output voltage set by register `0x49` Bit[14:3], OTG power-good OTGPG asserts to high. Control2 register Bit[5] can also be used to turn the ASGATE FET off to cut off the OTG output.
+
+Before OTG mode starts switching, the CSIP pin voltage needs to drop below the OTG output overvoltage protection threshold (OTG Voltage DAC(`0x49h`) + 1.8V) first. The CSIP pin is the output sensing point in OTG mode.
+
+The default OTG output voltage is 5.004V. The OTG Voltage register `0x49h` configure the OTG output voltage.
+
+The default OTG output current is 512mA when R<sub>s1</sub> is 10mΩ. The OTG Current register `0x4Ah` can be used to adjust the OTG output current limit.
+
+The RAA489118 includes the OTG output undervoltage and overvoltage protection functions. The UVP threshold is OTG output voltage -1.8V and the OVP threshold is OTG output voltage +1.8V.
+
+When UV is detected, the RAA489118 de-asserts OTGPG. After 32ms, it stops switching and turns off ASGATE. It resumes switching after the debounce time set by Control2 register Bit[13] and Control3 register Bit[0].
+
+When OV is detected, the RAA489118 de-asserts OTGPG. It resumes switching when the OTG voltage drops below the OTG Voltage DAC value specified at `0x49`.
+
+BATGONE must be low to enable OTG mode.
+
+<!-- page 46 -->
+
+## 7.3 Pass-Through Mode
+
+Pass-Through Mode (PTM) is configured by Control2 register Bits[1:0]. When PTM (normal or forced) is enabled, the internal reference for the output voltage ramps to the input voltage, and switching continues until the output voltage is within ±150mV of the input (adapter) voltage. Once the output voltage falls within this 300mV window, switching stops, Q1 and Q4 are set on, and Q2 and Q3 are turned off. When PTM is enabled, all protections are still active.
+
+To disable PTM, set Control2 register Bits[1:0] = 00. On exiting PTM, the internal reference for the output voltage ramps to the MaximumSystemVoltage DAC value, and switching resumes. Normal PTM is also exited if any of the following criteria are encountered:
+
+- Adapter OV triggers
+- Ideal Diode Mode is entered
+- The battery discharge current exceeds 600mA (for RS2 = 5mΩ)
+- VSYS absolute OV triggers
+
+Forced PTM can only be exited by disabling PTM using Control2 Bits[1:0].
+
+Before entering Pass-Through mode, the following is recommended:
+
+1. Ensure CV mode operation;
+2. Enable slew rate limiting by setting Control6 Bit[6] = 1; and
+3. Change the MaximumSystemVoltage DAC to a value as close to the V<sub>ADP</sub> voltage as possible.
+
+When Q1 and Q4 are latching on to enter Pass-Through mode, the adapter current limit loop turns on for more than 1ms.
+
+## 7.4 Modulator Control Loops
+
+Figure 40 shows the modulator's four main control loops. Each loop has a DAC register to provide settings as needed for each system.
+
+**Figure 40. Charger Control Loops**
+
+![Figure 40. Charger Control Loops](07-modulator-information/figure-40.png)
+
+<!-- page 47 -->
+
+### 7.4.1 Adapter Current Loop and Two-Level Current Limit
+
+To set the adapter current limit, write a 16-bit AdapterCurrentLimit1 command to register address `0x3FH` and, optionally, an AdapterCurrentLimit2 command to register address `0x3BH` using the Write-word protocol. See Table 2 for the DAC summary of values.
+
+The RAA489118 limits the adapter current by limiting the CSIP - CSIN voltage. By using the recommended R<sub>S1</sub> current sense resistor of 10mΩ, the LSB of the register translates to 8mA of adapter current.
+
+After adapter POR, the AdapterCurrentLimit1 register is reset to the value programmed through the PROG pin resistor. The AdapterCurrentLimit2 register is set to its default value of 1.504A or keeps the value that is written to it previously if the battery is present first. The AdapterCurrentLimit1 and AdapterCurrentLimit2 registers can be read back to verify their content. By default, the two level adapter current limit is disabled.
+
+The AdapterCurrentLimit2 register has the same specification as the AdapterCurrentLimit1 register.
+
+The two-level adapter current limit function can be enabled and disabled through SMBus Control2 register Bit[12] and the t1, t2 settings are configured by the Control5 register. When the two-level adapter current limit function is disabled, only the AdapterCurrentLimit1 value is used as the adapter current limit and AdapterCurrentLimit2 value is ignored.
+
+In a real system, a Turbo event usually does not last very long. It is often no longer than milliseconds, a time length during which the adapter can supply current higher than its DC rating. The RAA489118 uses a two-level adapter current limit to fully take advantage of the surge capability of the adapter and minimize the power drawn from the battery.
+
+Figure 41 shows the two SMBus programmable adapter current limit levels, AdapterCurrentLimit1 and AdapterCurrentLimit2, as well as the durations t1 and t2. The two-level adapter current limit function is initiated when the adapter current is less than 100mA lower than the AdapterCurrentLimit1 register setting. It starts at AdapterCurrentLimit2 for duration t2, then changes to AdapterCurrentLimit1 for duration t1 before repeating the pattern. These parameters can set the adapter current limit with an envelope that allows the adapter to temporarily output surge current without requiring the charger to enter Turbo mode. This operation maximizes battery life.
+
+The AdapterCurrentLimit1 register value can be higher or lower than the AdapterCurrentLimit2 value.
+
+**Figure 41. Two-Level Adapter Current Limit**
+
+![Figure 41. Two-Level Adapter Current Limit](07-modulator-information/figure-41.png)
+
+<!-- page 48 -->
+
+### 7.4.2 USB-PD On-the-Go Output Current
+
+The OTG output current regulation register DAC (Table 2) contains the SMBus readable and writable current that the current sense loop tries to regulate. This loop reuses the input current sense amplifier. If you are using the USB-PD Programmable Power Supply, this is the current limit loop. *Note*: Renesas recommends disabling OTG undervoltage protection when OTG current limiting mode is anticipated as part of normal operation.
+
+### 7.4.3 Input Voltage Regulation Loop
+
+#### 7.4.3.1 Adapter Minimum Voltage
+
+The input voltage regulation register DAC (Table 2) contains the SMBus readable and writable input voltage limit at which the input voltage loop tries to regulate when the input voltage is dropping. When the ADP is browning out or weak, the input voltage can droop and the input voltage loop tries to regulate to this setting by reducing battery charging current and then system power to try to hold up the input voltage. The system voltage might start to drop if the input power is not high enough to support the system.
+
+#### 7.4.3.2 USB-PD On-the-Go Minimum Battery Voltage
+
+The input voltage regulation register DAC (Table 2) sets a minimum voltage for VBAT when operating in OTG mode. Control5 register Bit[11] enables and disables the battery voltage (VBAT) regulation loop. This regulation loop can be used to prevent over-discharging of a battery when operating in OTG mode (for example, USB-PD source mode).
+
+### 7.4.4 USB-PD On-the-Go Output Voltage
+
+The OTG output voltage regulation register DAC (Table 2) contains the SMBus readable and writable voltage that the voltage loop tries to regulate. This loop reuses the input voltage sense amp.
+
+This register accepts any voltage value, but only the valid register bits are written to the register. The maximum value is clamped.
+
+### 7.4.5 System Voltage Regulation and Trickle Charging
+
+This loop works with two different voltage settings, MaxSystemVoltage and MinSystemVoltage.
+
+The MaxSystemVoltage register sets the battery full charging voltage limit. In NVDC charging mode, the MaximumSystemVoltage register setting is also the system bus voltage regulation point when the battery is absent or when the battery is present but not in Charging mode.
+
+The VSYS pin senses the battery voltage for maximum charging voltage regulation. The VSYS pin is also the system bus voltage regulation sense point.
+
+If the battery is absent, the BGATE is turned off (no charging) and the system voltage is regulated to the same setting as the MaxSystemVoltage DAC(`0x15h`). To set the maximum charging voltage or the system regulating voltage, write a 16-bit MaxSystemVoltage command to register address `0x15H` using the Write-word protocol shown in Figure 37.
+
+The RAA489118 supports trickle charging to overly discharged batteries. It can activate the trickle charging function when the battery voltage is lower than MinSystemVoltage setting. The VBAT pin is the battery voltage sense point for Trickle Charge mode.
+
+To enable Trickle Charging, set the ChargeCurrent register to a non-zero value. To disable trickle charging, set the ChargeCurrent register to 0. See Table 15 for trickle charging control logic.
+
+The trickle charging current can be programmed to be 1024mA, 512mA, 256mA, or 128mA (with 5mΩ R<sub>s2</sub>) through SMBus Control2 register Bit[15:14] as shown in Table 5.
+
+In Trickle Charging mode, the RAA489118 regulates the trickle charging current through the buck-boost switcher. Provided that a BFET is present, another independent control loop drives the BFET gate so that the system voltage is maintained at the voltage set in the MinSystemVoltage register. If there is no BFET, the system voltage
+
+<!-- page 49 -->
+
+might fall below the MinSystemVoltage setting. The VSYS pin is the system voltage sensing point in Trickle Charging mode.
+
+When the battery voltage is charged to the MinSystemVoltage register value, the RAA489118 enters Fast Charging mode by limiting the charging current at the ChargeCurrentLimit register setting, which is typically higher than the trickle charge current.
+
+### 7.4.6 Charging Current Loop
+
+This loop uses the charge current DAC (see Table 2) to set the fast charging current limit. To set it, write a 16-bit ChargeCurrentLimit command to register address `0x14H` (Table 1).
+
+The RAA489118 limits the charging current by limiting the CSOP - CSON voltage. Therefore, the charge current depends on the R<sub>s2</sub> resistor value. For example, if the current sense resistor R<sub>s2</sub> is halved, the regulated charge current doubles. By using the current sense resistor R<sub>s2</sub> = 5mΩ, the LSB of the register translates to 8mA of charging current. The ChargeCurrentLimit register accepts any charging current command, but only the valid register bits are written to the register.
+
+#### 7.4.6.1 Reverse Mode Discharge Current
+
+When the charger is in reverse mode of operation (OTG), there is a discharge current limit loop that is set by 2x the Charge Current limit register (`0x14`). This discharge current limit loop is in addition to the voltage regulation loop set by the OTG Voltage register, the current limit loop set by the OTG Current register, and the optional VBAT regulation loop set by the Input Voltage register. The discharge current limit loop is disabled when charge current limit (`0x14h`) is zero. When the charge current is a non-zero value, the charger limits the battery discharge current to be less than the discharge current limit (2x the Charge Current limit). This function can be used to limit inrush current from the battery when the OTG Voltage ramps up or down (in addition to the slew rate function).
+
+### 7.4.7 Turbo Mode Support
+
+Turbo mode refers to the system drawing more power than the power rating of the adapter.
+
+If the adapter current reaches the AdapterCurrentLimit1 register set value (or the AdapterCurrentLimit2 register set value, if the two-level adapter current limit function is enabled), or the adapter input voltage drops to the Input Voltage Regulation Reference set by Input Voltage DAC register (`0x4B`), the RAA489118 limits the input power by regulating the adapter current at the AdapterCurrentLimit1/2 register set value, or by regulating the adapter voltage at the Input Voltage Regulation Reference point.
+
+In Turbo mode, the system bus voltage VSYS drops automatically or the charging current drops automatically to limit the adapter input power. If the VSYS pin voltage is 150mV lower than the VBAT pin voltage, the BGATE FET turns on so that the battery supplies the rest of the power required by the system.
+
+If the RAA489118 detects 250mA charging current or if the battery discharging current is less than 380mA for longer than the IDM exit timeout (80ms, 40ms, 5ms, or 1 ms), BGATE turns off and Turbo mode exits. The Turbo mode exit timer is configured through Control3 register `0x4C` Bit[8] and Control7 register `0x36` Bit[7]. See Table 15 for BGATE control logic.
+
+**Table 15. BGATE On/Off Truth Table**
+
+| Turbo (Control Bit)<br>**0 = Enable**<br>**1 = Disable** | ChargeCurrent Register<br>**0 = Zero**<br>**1 = Nonzero** | BGATE On/Off<br>**System Load Not In Turbo Mode Range** | BGATE On/Off<br>**System Load in Turbo Mode Range** |
+| --- | --- | --- | --- |
+| 0 | 0 | OFF | ON |
+| 0 | 1 | ON for fast charge; Trickle charge is enabled | ON |
+| 1 | 0 | OFF | OFF |
+| 1 | 1 | ON for fast charge; Trickle charge is enabled | ON |
+
+<!-- page 50 -->
+
+## 7.5 R3 Modulator
+
+The RAA489118 uses the patented Renesas Robust Ripple Regulator (R3) modulation scheme. The R3 modulator combines the best features of fixed frequency PWM and hysteretic PWM while eliminating many of their shortcomings. Figure 42 conceptually shows the R3 modulator circuit, and Figure 43 shows the operation principles in steady state.
+
+**Figure 42. R3 Modulator**
+
+![Figure 42. R3 Modulator](07-modulator-information/figure-42.png)
+
+**Figure 43. R3 Modulator Operation Principles In Steady State**
+
+![Figure 43. R3 Modulator Operation Principles In Steady State](07-modulator-information/figure-43.png)
+
+A fixed voltage window (VW window) exists between VW and COMP. The modulator charges the ripple capacitor C<sub>R</sub> with a current source equal to g<sub>m</sub>(V<sub>IN</sub> - V<sub>O</sub>) during PWM on-time and discharges the ripple capacitor C<sub>R</sub> with a current source equal to g<sub>m</sub>V<sub>O</sub> during PWM off-time, where g<sub>m</sub> is a gain factor. The C<sub>R</sub> voltage V<sub>CR</sub> therefore emulates the inductor current waveform. The modulator turns off the PWM pulse when V<sub>CR</sub> reaches VW and turns on the PWM pulse when it reaches COMP.
+
+Because the modulator works with V<sub>CR</sub>, which is large amplitude and noise free synthesized signal, it achieves lower phase jitter than conventional hysteretic mode modulator.
+
+Figure 44 shows the operation principles during dynamic response. The COMP voltage rises during dynamic response, turning on PWM pulses earlier and more frequently temporarily, which allows for higher control loop bandwidth than conventional fixed frequency PWM modulators at the same steady state switching frequency.
+
+<!-- page 51 -->
+
+**Figure 44. R3 Modulator Operation Principles In Dynamic Response**
+
+![Figure 44. R3 Modulator Operation Principles In Dynamic Response](07-modulator-information/figure-44.png)
+
+The R3 modulator can operate in Diode Emulation (DE) mode to increase light-load efficiency. In DE mode, the low-side MOSFET conducts when the current is flowing from source-to-drain and does not allow reverse current, which emulates a diode. As shown in Figure 45, when LGATE is on, the low-side MOSFET carries current and creates negative voltage on the phase node due to the voltage drop across the ON-resistance. The IC monitors the current by monitoring the phase node voltage. It turns off LGATE when the phase node voltage reaches zero to prevent the inductor current from reversing the direction and creating unnecessary power loss.
+
+**Figure 45. Diode Emulation**
+
+![Figure 45. Diode Emulation](07-modulator-information/figure-45.png)
+
+If the load current is light enough, as Figure 45 shows, the inductor current reaches and stays at zero before the next phase node pulse, and the regulator is in Discontinuous Conduction Mode (DCM). If the load current is heavy enough, the inductor current never reaches 0A, and the regulator is in Continuous Conduction Mode (CCM) although the controller is in DE mode.
+
+Figure 46 shows the operation principle in DE mode at light load. The load gets incrementally lighter in the three cases from top to bottom. The PWM on-time is determined by the VW window size and therefore is the same, so the inductor current triangle is the same in the three cases. The R3 modulator clamps the ripple capacitor voltage V<sub>CR</sub> in DE mode to mimic the inductor current. The COMP voltage takes longer to reach V<sub>CR</sub>, which naturally stretches the switching period. The inductor current triangles move farther apart from each other so that the inductor current average value is equal to the load current. The reduced switching frequency helps increase light-load efficiency.

REN_RAA489118/08-application-information.md

@@ -0,0 +1,314 @@
+<!-- page 52 -->
+
+**Figure 46. Period Stretching**
+
+![Figure 46. Period Stretching](08-application-information/figure-46.png)
+
+# 8. Application Information
+
+## 8.1 Soft-Start
+
+The RAA489118 includes a low power LDO with nominal 4.6V output, with an input OR-ed from the VBAT and ADP pins. The RAA489118 also includes a high power LDO with nominal 5V output, with an input from the DCIN pin, which connects to both the adapter and the system bus through an external OR-ing diode circuit. Both LDO outputs are tied to the VDD pin to provide the bias power and gate drive power for the RAA489118. The VDDP pin is the RAA489118 gate drive power supply input. Use an R-C filter to generate the VDDP pin voltage from the VDD pin voltage.
+
+When V<sub>DD</sub> > 2.7V, the digital block is activated and the SMBus register is ready to communicate with the master controller.
+
+With VADP >3.2V and after the 1.3s or 150ms debounce time, the RAA489118 uses a patented Renesas technique to check whether the input bus is shorted. If CSIP <2V or ACIN <0.8V, ASGATE does not turn on. The input bus short protection adds an additional few milliseconds of delay, wherein the delay depends on the input capacitance. For adapter insertions after the initial one, the debounce time of 1.3s or 150ms is set by Control2 register Bit[11]. The debounce time for an initial adapter insertion is always 150ms. After the debounce time and the input bus short check, ASGATE starts turning on with 10µA of sink current.
+
+Use a voltage divider from the adapter voltage to set the ACIN pin voltage. The RAA489118 monitors the ACIN pin voltage to determine the presence of the adapter. When V<sub>DD</sub> > 3.8V, the ACIN pin voltage exceeds 0.6V, and ASGATE is fully turned on, the RAA489118 allows the external circuit to pull up the ACOK pin. When ACOK is asserted, the RAA489118 starts switching.
+
+The ACOK is an open-drain output pin that indicates the presence and readiness of the adapter to supply power to the system bus. The RAA489118 actively pulls ACOK low in the absence of the adapter.
+
+Before ASGATE turns ON, the RAA489118 sources 10µA of current out of the PROG pin and reads the pin voltage to determine the PROG resistor value. The PROG resistor programs the configurations of the RAA489118.
+
+In Battery Only mode, the RAA489118 enters Low Power mode if only the battery is present. V<sub>DD</sub> is 4.6V from the low power LDO to minimize power consumption.
+
+<!-- page 53 -->
+
+## 8.2 Charging Mode Configuration
+
+The RAA489118 can be configured to support a battery-charging-only application with no requirement for a battery FET (BFET). Connecting the `CONFIG/PSYS` pin to VDD configures the Buck-Boost charger to operate with no BFET. To configure the RAA489118 to support operation with a BFET, the `CONFIG/PSYS` pin should be pulled to ground with a PSYS resistor. For this case, the `CONFIG/PSYS` pin provides PSYS functionality.
+
+- `CONFIG/PSYS` tied to VDD: Battery-charging-only mode with no BFET
+- `CONFIG/PSYS` connected to PSYS resistor: NVDC charging with BFET support
+
+### 8.2.1 Battery Charging Only (no BFET)
+
+Figure 2 provides a circuit topology for an application that has no BFET, and which only provides battery charging. With no BFET, the system bus (VSYS) cannot be isolated from the battery (VBAT), and VSYS cannot be regulated separately from VBAT. With `CONFIG/PSYS` tied to VDD, the Buck-Boost charger is configured to support such a battery-charging-only application that has no BFET.
+
+At POR with `CONFIG/PSYS` tied to VDD, the Charge Current (CC) DAC register (`0x14`) is initialized to 256mA (presuming R<sub>s2</sub> = 5 mΩ), and the charging mode is set for SMBus control (Control3 Bit[7] = 1). This causes the Buck-Boost charger to begin operation by charging an attached battery at the relatively low level of 256 mA. In typical usage, the charge current would be increased after initialization by writing a new value to the CC DAC register (`0x14`).
+
+In battery-charging-only mode, there is no SMBus timeout function. Charging continues indefinitely and does not require any I<sup>2</sup>C interaction.
+
+*Note*: Maintain the CC register at a nonzero value, because setting CC to zero disables the charge current limit.
+
+### 8.2.2 NVDC Charging (with BFET)
+
+Figure 3 provides a circuit topology for an application that has a BFET, which supports NVDC battery charging. The BFET provides the ability to isolate the system bus (VSYS) from the battery (VBAT), such that VSYS can be regulated independently of VBAT. With `CONFIG/PSYS` connected to a PSYS resistor, the Buck-Boost charger supports NVDC charging with a BFET.
+
+If `CONFIG/PSYS` is connected to a PSYS resistor, the Charge Current DAC register (`0x14`) is initialized with 0A at POR. The BFET is turned off so that there is no battery charge current. The Buck-Boost charger initializes to CV control, such that VSYS is regulated at the MaxSystemVoltage level. Battery charging can be subsequently enabled by writing a nonzero value to the CC DAC register (`0x14`).
+
+## 8.3 Programming Charger Option
+
+The resistor from the PROG pin to GND programs the default number of battery cells in series, the default AdapterCurrentLimit1 register value, and the autonomous charging function. Table 16 shows the programming options.
+
+<!-- page 54 -->
+
+**Table 16. PROG Pin Programming Options**
+
+| PROG-GND Resistance (kΩ) — Min | PROG-GND Resistance (kΩ) — Typ. 1% | PROG-GND Resistance (kΩ) — Max | Min V<sub>SYS</sub> (V) | Max V<sub>SYS</sub> (V) | Autonomous Charging[1] | Default ACLimit1 Reg (A) |
+| --- | --- | --- | --- | --- | --- | --- |
+| 42.7 | 43.2 | 43.7 | 5.12 | 8.400 | Yes | 1.504 |
+| 51.7 | 52.3 | 52.9 | 5.12 | 8.400 | No | 1.504 |
+| 61.2 | 61.9 | 62.6 | 5.12 | 8.400 | No | 0.48 |
+| 70.6 | 71.5 | 72.4 | 7.68 | 12.608 | Yes | 1.504 |
+| 81.5 | 82.5 | 83.5 | 7.68 | 12.608 | No | 1.504 |
+| 92 | 93.1 | 94.2 | 7.68 | 12.608 | No | 0.48 |
+| 104 | 105 | 106 | 10.24 | 16.800 | Yes | 1.504 |
+| 116 | 118 | 120 | 10.24 | 16.800 | No | 1.504 |
+| 131 | 133 | 135 | 10.24 | 16.800 | No | 0.48 |
+| 145 | 147 | 149 | 12.80 | 21.008 | Yes | 1.504 |
+| 160 | 162 | 164 | 12.80 | 21.008 | No | 1.504 |
+| 176 | 178 | 180 | 12.80 | 21.008 | No | 0.48 |
+| 194 | 196 | 198 | 15.36 | 25.200 | Yes | 1.504 |
+| 212 | 215 | 218 | 15.36 | 25.200 | No | 1.504 |
+| 234 | 237 | 240 | 15.36 | 25.200 | No | 0.48 |
+| 258 | 261 | 264 | 17.92 | 29.408 | Yes | 1.504 |
+| 284 | 287 | 290 | 17.92 | 29.408 | No | 1.504 |
+| 312 | 316 | 320 | 17.92 | 29.408 | No | 0.48 |
+
+1. Autonomous charging mode is only configured if CONGIG/PSYS pin is pulled low at POR. If CONFIG/PSYS is tied high at POR, the charging mode is set to SMBus Charging regardless of the PROG resistance.
+
+RAA489118 uses the default MaxVsystemVoltage register values in Table 1. The default switching frequency is 732kHz. If PSYS function is used, battery cell numbers can be mapped as 2/3/4/5/6/7cells versus 8.4/12.6/16.8/21/25.2/29.4V accordingly in Table 1.
+
+The switching frequency can be changed through SMBus Control1 register Bit[9:8] after POR. See the SMBus Control1 register programming table (Table 4) for a detailed description.
+
+Before ASGATE turns on, the RAA489118 sources 10µA of current out of the PROG pin and reads the PROG pin voltage to determine the resistor value. However, application environmental noise can pollute the PROG pin voltage and cause incorrect readings. If noise is a concern, connect a capacitor from the PROG pin to GND to provide filtering. The resistor and the capacitor RC time constant should be less than 40µs so the PROG pin voltage can rise to steady state before the RAA489118 reads it.
+
+If the RAA489118 is powered up from the battery, it does not read the PROG resistor unless PSYS is enabled through SMBus Control1 register Bit[3]. Whenever PSYS is enabled in Battery Only mode, the RAA489118 reads the PROG pin resistor and resets the configuration to the default.
+
+When the adapter is plugged in, the RAA489118 resets the AdapterCurrentLimit1 register to the default by reading the PROG pin resistor if it was not read before, or by loading the previous readings. If PSYS is not enabled, the RAA489118 resets the MaxSystemVoltage register and MinSystemVoltage register to their default values according to the PROG pin setting. If PSYS is enabled, the RAA489118 keeps the values in these two registers.
+
+<!-- page 55 -->
+
+By default, the adapter current sensing resistor R<sub>s1</sub> is 10mΩ and the battery current sensing resistor R<sub>s2</sub> is 5mΩ. Using this R<sub>1</sub> = 10mΩ and R<sub>s2</sub> = 5mΩ option results in an 8mA/LSB correlation in the SMBus current commands. If the R<sub>s1</sub> and R<sub>s2</sub> differ from these default options, the SMBus command needs to be scaled accordingly to obtain the correct current. Smaller current sense resistor values reduce power loss while larger current sense resistor values give better accuracy.
+
+## 8.4 Autonomous Charging Mode
+
+Autonomous charging mode is only available in the NVDC charging configuration (`CONFIG/PSYS` pin pulled low at POR).
+
+Autonomous Charging mode can be enabled or disabled through the programming charging option resistor or SMBus Control3 register Bit[7]. When Autonomous Charging mode is enabled, this mode can also be disabled by writing to the SMBus ChargeCurrentLimit or MaxSystemVoltage registers.
+
+The RAA489118 enters Autonomous Charging mode when both the battery voltage is lower than MaxSystemVoltage - 180mV per cell for 1ms of debounce time and the BGATE MOSFET is on.
+
+In Autonomous Charging mode, the RAA489118 starts to charge the battery with 4A (with R<sub>S2</sub> = 5mΩ), the `PROCHOT#` pin (Autonomous Charging mode indication pin) is pulled down to GND, and the SMBus charging timeout timer is disabled. The RAA489118 exits from Autonomous Charging mode when the battery charging current is less than 280mA (with R<sub>S2</sub> = 5mΩ) for 20ms or 200ms in CV loop. The autonomous charging termination time can be set by Control3 register Bit[13]. The RAA489118 re-enters Autonomous Charging mode when the battery voltage is discharged below MaxSystemVoltage - 180mV per cell. When the RAA489118 stays in Autonomous Charging mode for 12hrs, which means the battery charging current is higher than 280mA and the battery cannot be charged to MaxSystemVoltage for 12hrs, the RAA489118 stops charging the battery and exits Autonomous Charging mode.
+
+## 8.5 Battery Ship Mode
+
+The RAA489118 supports Battery Ship mode. When Control3 register Bit[10] is 1, the BGATE MOSFET stays off for Battery Ship mode.
+
+Battery Ship mode sets the lowest power state for the IC. Ship mode can only be entered from Battery Only mode. To achieve the lowest power, several analog functions must be disabled. Many are disabled by default and do not need to be written, but all are listed for completeness. However, the power level can be customized for the system.
+
+- Control1 `0x3C`
+  - Bit[5] = 1 Disable IMON
+  - Bit[3] = 0 Disable PSYS
+- Control2 `0x3D`
+  - Bit[3] = 1 Disable GP Comparator
+- Control3 `0x4C`
+  - Bit[10] = 1 Force BGATE Off
+
+To exit Battery Ship mode, use the SMBus to change the control bits.
+
+## 8.6 Diode Emulation Operation
+
+In Diode Emulation (DE) mode, the RAA489118 uses a phase comparator to monitor the PHASE node voltage during the low-side switching FET on-time to detect the inductor current zero crossing. The phase comparator needs a minimum on-time of the low-side switching FET to recognize inductor current zero crossing. If the low-side switching FET on-time is too short for the phase comparator to successfully recognize the inductor zero crossing, the RAA489118 can lose DE ability. To prevent this, the RAA489118 uses a minimum low-side switching FET on-time. When the intended low-side switching FET on-time is shorter than the minimum value, the
+
+<!-- page 56 -->
+
+RAA489118 stretches the switching period to keep the low-side switching FET on-time at the minimum value, which causes the CCM switching frequency to drop below the set point.
+
+## 8.7 Battery Learn Mode
+
+Use Battery Learn mode to supply the system power from the battery even when the adapter is plugged in, such as calibration of the battery fuel gauge.
+
+The RAA489118 enters Battery Learn mode when it receives the SMBus Control command. When entering Battery Learn mode, the RAA489118 turns on the BGATE FET.
+
+In Battery Learn mode, the RAA489118 turns on BGATE and keeps ASGATE on but turns off the buck-boost switcher regardless of whether the adapter is present.
+
+The three ways of exiting Battery Learn mode are:
+
+- Receive the Battery Learn mode exit command through SMBus
+- The battery voltage is less than MinSystemVoltage register setting and Control1 Bit[13] = 1
+- The `BATGONE` pin voltage goes from logic LOW to HIGH
+
+In all these cases, the RAA489118 resumes switching immediately to supply power to the system bus from the adapter to prevent system voltage collapse.
+
+Renesas recommends to disable the slew rate control (Control6 Bit[6] = 0) when using Learn mode.
+
+## 8.8 Charger Timeout
+
+The RAA489118 includes a timer to ensure the SMBus master is active and to prevent overcharging the battery. The charger timeout functionality is only available in the NVDC charging configuration (`CONFIG/PSYS` pulled low with PSYS resistor). The RAA489118 terminates charging by turning off the BGATE FET if the charger has not received a write command to the MaxSystemVoltage or ChargeCurrent register within 175s (SMBus Control3 register Bit[12:11] = 00). The charger timeout time can be configured through SMBus Control3 register Bit[12:11]. When charging is terminated by the timeout, the ChargeCurrent register retains its value instead of resetting to zero. If a timeout occurs, the MaxSystemVoltage or ChargeCurrent register must be written to re-enable charging.
+
+The charger timeout function can be disabled using SMBus Control0 register Bit[7] as shown Table 3.
+
+## 8.9 Monitoring
+
+### 8.9.1 Current Monitor
+
+The RAA489118 provides an adapter current monitor/OTG current monitor or a battery charging current monitor/battery discharging current monitor through the `AMON/BMON` pin. The AMON output voltage is 18x (`CSIP` - `CSIN`) and 18x (`CSIN` - `CSIP`) voltage. The BMON output voltage is 18x (`CSON` - `CSOP`) and 36x (`CSOP` - `CSON`) voltage.
+
+The AMON and BMON functions can be enabled or disabled through SMBus Control1 register Bit[5]. AMON or BMON can be selected through SMBus Control1 register Bit[4] and the AMON/BMON direction can be configured through SMBus Control3 register Bit[3] as Table 4 shows.
+
+### 8.9.2 PSYS Monitor
+
+The RAA489118 PSYS pin provides a measure of the instantaneous power consumption of the entire platform. The PSYS pin outputs a current source described by Equation 1.
+
+(EQ. 1) $I_{PSYS} = K_{PSYS} \times (V_{ADP} \times I_{ADP} + V_{BAT} \times I_{BAT})$
+
+K<sub>PSYS</sub> is based on the current sensing resistor R<sub>s1</sub> = 10mΩ and R<sub>s2</sub> = 5mΩ. V<sub>ADP</sub> is the adapter voltage in V, I<sub>ADP</sub> is the adapter current in A, V<sub>BAT</sub> is the battery voltage, and I<sub>BAT</sub> is the battery discharging current. When the
+
+<!-- page 57 -->
+
+battery is discharging, I<sub>BAT</sub> is a positive value; when the battery is being charged, I<sub>BAT</sub> is a negative value. The battery voltage V<sub>BAT</sub> is detected through the `CSON` pin to maximize the power monitor accuracy in NVDC configuration Trickle Charge mode.
+
+The R<sub>s1</sub> to R<sub>s2</sub> ratio must be 2:1 for valid power calculation. If the resistance values are higher (or lower) than the suggested values mentioned previously, K<sub>PSYS</sub> is proportionally higher (or lower). As an example, if R<sub>s1</sub> = 5mΩ and R<sub>s2</sub> = 2.5mΩ, the output current is half that above for the same power. If the PSYS information is not needed, any R<sub>s1</sub>:R<sub>s2</sub> ratio is acceptable.
+
+The default PSYS gain is set to 0.236µA/W, and can be configured through SMBus Control3 register Bit[9].
+
+The PSYS information includes the power loss of the charger circuit and the actual power delivered to the system. The resistor R<sub>PSYS</sub> connected between the PSYS pin and GND converts the PSYS information from current to voltage.
+
+PSYS accuracy limits and a typical accuracy scan are shown in Figure 47.
+
+**Figure 47. PSYS Accuracy and Limits**
+
+![Figure 47. PSYS Accuracy and Limits](08-application-information/figure-47.png)
+
+The PSYS function can be enabled or disabled through SMBus Control1 register Bit[3] as shown in Table 4.
+
+### 8.9.3 PROCHOT#
+
+`PROCHOT#` is an open-drain output used to support IMVP protocols. A `PROCHOT#` assertion is triggered if the adapter current exceeds the ACProchot# threshold, the battery discharge current exceeds a discharge current threshold, or VSYS falls below the Low_VSYS_Prochot# threshold. `PROCHOT#` can also, optionally, be asserted if the OTG Current exceeds a threshold, or by the BATGONE, ACOK, or General Purpose Comparator signals.
+
+In Autonomous Charging mode, the `PROCHOT#` pin behaves as an indication pin and is pulled down to GND while autonomous-mode charging is active.
+
+#### 8.9.3.1 PROCHOT# for Adapter Overcurrent Conditions
+
+To set the `PROCHOT#` assertion threshold for adapter overcurrent conditions, write a 16-bit ACProchot# command to register address `0x47` using the Write-word protocol shown in Figure 37 and the data format shown in Table 2. The ACProchot# register can be read back to verify its contents.
+
+If the adapter current exceeds the ACProchot# register setting, the `PROCHOT#` signal asserts after the debounce time set by Control2 register Bit[10:9]. The `PROCHOT#` signal remains asserted for a minimum duration set by Control2 register Bit[8:6].
+
+#### 8.9.3.2 PROCHOT# for Battery Over Discharging Current Conditions
+
+The threshold for the `PROCHOT#` Battery over-discharge condition depends on whether the battery charger is in low-power battery-only mode or in normal mode.
+
+<!-- page 58 -->
+
+In normal mode, the `PROCHOT#` signal assertion threshold for battery over discharging current conditions is set by the DCProchot# value in DAC register `0x48`.
+
+In battery-only low-power mode with PSYS disabled, the battery over-discharging threshold is set by the DCProchot# level configured by Control0 register Bit[4:3] and Control7 register Bit[1]. However, if PSYS is enabled, the DCProchot# threshold is set by the value in DAC register `0x48`.
+
+If the battery discharging current exceeds the DCProchot# threshold, as set by the DCProchot# DAC register `0x48` or Control0 register Bit[4:3] and Control7 register Bit[1], the `PROCHOT#` signal asserts after the debounce time programmed by Control2 register Bit[10:9]. The `PROCHOT#` signal remains asserted for a minimum duration time determined by Control2 register Bit[8:6].
+
+#### 8.9.3.3 Low_VSYS_Prochot#
+
+The Low_VSYS_Prochot# threshold is configured using Control1 register Bit[1:0], which provides four threshold settings. In battery-only mode, Low_VSYS_Prochot# only works if PSYS, or OTG is enabled.
+
+#### 8.9.3.4 Other PROCHOT# Triggers
+
+The `PROCHOT#` signal can also be asserted if the OTG current is excessive, if BATGONE goes high (indicating no battery), if ACOK goes low (indicating no adapter) or if the General-Purpose Comparator triggers. Control4 Bits[7:4] are used to enable these additional `PROCHOT#` triggers. The OTGCurrent `PROCHOT#` threshold is the same as the adapter current `PROCHOT#` threshold ACProchot# specified in DAC register `0x48`.
+
+#### 8.9.3.5 Setting PROCHOT# Debounce Time and Duration Time
+
+The `PROCHOT#` signal debounce time for ACProchot# and DCProchot# is set by Control2 register Bit[10:9]. The low system (VSYS_LOW) voltage `PROCHOT#` has a fixed debounce time of 7µs.
+
+The minimum duration of a `PROCHOT#` assertion triggered by Low_VSYS, ACProchot#, or DCProchot# is set by Control2 register Bit[8:6].
+
+The debounce time for `PROCHOT#` assertions triggered by ACOK and BATGONE is set by Control4 register Bit[3:2].
+
+#### 8.9.3.6 Setting PROCHOT# Clear and Latch Control Bits
+
+Control4 Bit[0] can be used to configure `PROCHOT#` to latch and hold its state. A latched `PROCHOT#` assertion can be cleared using Control4 Bit[1].
+
+## 8.10 Stand-Alone Comparator
+
+The RAA489118 includes a general purpose stand-alone comparator. The `OTGEN/CMIN` pin is the comparator input. The internal comparator reference is connected to the inverting input of the comparator and can be configured as 1.2V or 2V through SMBus Control2 register Bit[4]. The comparator output is the `OTGPG/CMOUT` pin. The output polarity can be configured through the SMBus register bit.
+
+- When Control2 register Bit[2] = 0 for normal comparator output polarity, CMOUT = High if CMIN > Reference; CMOUT = Low if CMIN < Reference.
+- When Control2 register Bit[2] = 1 for inversed comparator output polarity, CMOUT = Low if CMIN > Reference; CMOUT = High if CMIN < Reference.
+
+By default in Battery Only mode, the stand-alone comparator is enabled. This comparator can be enabled/disabled in Battery Only mode using Control 2 Bit[3]. In Battery Only mode, the reference is always 1.2V, regardless of the value of Control2 Bit[4].
+
+Table 17 shows the OTG mode and the stand-alone comparator truth table.
+
+<!-- page 59 -->
+
+**Table 17. OTG and Comparator Truth Table**
+
+| Control1 Bit[11] OTG Function Enable/Disable | Control2 Bit[3] GP Comparator Enable/Disable | PIN-20 `OTGEN/CMIN` | PIN-26 `OTGPG/CMOUT` | Description |
+| --- | --- | --- | --- | --- |
+| 0 | 0 | Comparator Input Pin CMIN | Comparator Output Pin CMOUT | OTG function is disabled. Comparator is enabled. |
+| 0 | 1 | X | X | Both the OTG function and comparator are disabled. |
+| 1 | 0 | Comparator Input Pin CMIN | Comparator Output Pin CMOUT | Both the OTG function and comparator are enabled. OTG function is enabled when V<sub>BAT</sub> > 4.5V and Control1 register Bit[11] = 1 without OTG power-good pin indication. The device is in OTG mode while Information1 register `0x3A` Bit[6:5] = 11. |
+| 1 | 1 | OTG Enable Input Pin OTGEN | OTG Power-Good Indication Pin OTGPG | Comparator is disabled. OTG function is enabled when V<sub>BAT</sub> > 4.5V and ENOTG pin = High and Control1 register Bit[11] = 1. |
+
+## 8.11 Protections[1]
+
+### 8.11.1 Adapter Overvoltage Protection
+
+If the ADP pin voltage exceeds 33.3V for more than 10µs, an adapter overvoltage condition occurs. The RAA489118 turns off the ASGATE MOSFETs to isolate the adapter from the system, de-asserts the ACOK signal by pulling it low, and stops switching. BGATE turns on for the battery to support the system load. When the ADP voltage drops below 32.7V from more than 100µs, it starts to turn on ASGATE and start switching.
+
+### 8.11.2 System Overvoltage Protection
+
+The RAA489118 provides system rail overvoltage protection. If the system voltage VSYS is 1.6V higher than MaxSystemVoltage register set value, it declares the system overvoltage and stops switching. It resumes switching with no debounce time when VSYS drops 800mV below the system overvoltage threshold.
+
+The RAA489118 provides VSYS absolute overvoltage protection. The absolute overvoltage rising threshold is 33.6V. If the system voltage VSYS is higher than 33.6V, it stops switching. When the VSYS drops to lower than 33.06V, it starts switching again.
+
+### 8.11.3 System Voltage Rail Short Protection
+
+The RAA489118 has a system rail short protection (VSYSOK) to prevent powering on the system rail into a short-circuit before switching starts. When the VSYS voltage is below 0.6V, the RAA489118 sources 10mA current (by default) from VDDP to charge VSYS before switching can start.
+
+From the beginning of VSYSOK (VSYS rail short protection) to the start of switching in the VSYS state, the parts must go through multiple startup and initialization transition states, including turning on ASGATE FET. This initialization transition duration might take longer than it takes to charge the VSYS voltage to 0.6V using a 10mA source by the VSYSOK function. If this initialization transition duration is longer than the duration of charging VSYS above 0.6V, the charger must wait until the transition duration is completed before switching starts, and vice versa.
+
+1. Nominal protection values are provided in this section. Refer to the Electrical Specifications for accurate values.
+
+<!-- page 60 -->
+
+Conversely, the duration of charging VSYS above 0.6V, which depends on the leakage current and capacitance value at VSYS, varies per individual system design. If estimating the duration in a worst-case scenario is required, Renesas recommends testing the design to determine the following:
+
+- If the initialization transition duration is longer than the duration of charging VSYS above 0.6V, add a 30% margin (considering ±5% clock tolerance) to estimate the duration.
+- If the initialization transition duration is shorter than the duration of charging VSYS above 0.6V, check the tolerance of the VSYS capacitance or leakage current from VSYS downstream circuitry and then add a reasonable margin, such as 40% (considering ±20% cap tolerance), to estimate the duration.
+
+After switching starts, the charger enters the Fault state if VSYS drops below 0.6V again at any time. After entering the Fault state, the charger stops switching and turns off ASGATE, and tries to start again with 1.3s or 150ms debounce time (configured by Control 2[11]).
+
+For RAA489118 startup without battery pack present, Renesas recommends ensuring that there is no load on VSYS at startup.
+
+After the initial POR, the VSYS rail short protection check can optionally be bypassed by disabling both the VSYSOK 0.6V Comparator using Control5 Bit[7] and the VSYSOK 10mA current source using Control5 Bit[6].
+
+### 8.11.4 System Voltage Undervoltage Protection (for Short-Circuit Protection)
+
+The charger has a fixed undervoltage protection on the system side that can be configured using Control 6[2:0].
+
+The initial value of the VSYS undervoltage is set as follows:
+
+- POR from battery: VSYS UV is 000 = disabled,
+- POR from adapter with CONFIG tied to VDD: VSYS UV is 000 = disabled,
+- POR from adapter with CONFIG pulled low: VSYS UV is 011 = 4.8V.
+
+When the VSYS voltage falls to the VSYS UV threshold set by Control 6[2:0], there is a 100ms debounce before the charger enters FAULT state. After entering FAULT state, there is no switching and charger tries to start switching again after the 150ms or 1.3s debounce time (configurable by Control 2[11]).
+
+### 8.11.5 Over-Temperature Protection
+
+The RAA489118 stops switching for self protection when the junction temperature exceeds +150°C. When the temperature falls below +130°C and after a 100µs delay, the RAA489118 resumes switching.
+
+## 8.12 Selecting the Power Source
+
+The RAA489118 automatically selects the adapter and/or the battery as the source for system power.
+
+The BGATE pin drives a P-channel MOSFET gate that connects/disconnects the battery from the system and the switcher.
+
+The ASGATE pin drives a pair of back-to-back common source P-channel MOSFETs to connect/disconnect the adapter from the system and the battery. Use of the ASGATE pin is optional.
+
+When the battery voltage V<sub>BAT</sub> is higher than 2.4V and the adapter voltage V<sub>ADP</sub> is less than 3.2V, the RAA489118 operates in Battery Only mode. During Battery Only mode, the RAA489118 turns on the BGATE FET to connect the battery to the system. In Battery Only mode, the RAA489118 consumes very low power (refer to the Battery Current specification). The battery discharging current monitor BMON can be turned on during this mode to monitor the battery discharging current. If the battery voltage V<sub>BAT</sub> is higher than 4.5V, the system power monitor PSYS function also can be turned on during this mode to monitor system power.
+
+In Battery Only mode, the USB OTG function can be enabled when the battery voltage V<sub>BAT</sub> is higher than 4.5V. See USB On-the-Go (USB OTG) for details.
+
+When the adapter voltage V<sub>ADP</sub> is more than 3.2V, the RAA489118 turns on ASGATE. If VDD is higher than 3.8V, the RAA489118 enters Forward Buck, Forward Boost, or Forward Buck-Boost mode depending on the adapter

REN_RAA489118/09-general-application-information.md

@@ -0,0 +1,150 @@
+<!-- page 61 -->
+
+and system voltage VSYS duty cycle ratio. The system bus voltage is regulated at the voltage set on the `MaxSystemVoltage` register. If the charge current register is programmed (non-zero), the RAA489118 charges the battery either in Trickle Charging mode or Fast Charging mode, as long as `BATGONE` is low.
+
+# 9. General Application Information
+
+This design guide provides a high-level explanation of the steps necessary to design a single-phase power converter. It is assumed that the reader is familiar with many of the basic skills and techniques referenced in the following sections. In addition to this guide, Renesas provides complete reference designs that include schematics, bill of materials, and example board layouts.
+
+## 9.1 Selecting the LC Output Filter
+
+The duty cycle of an ideal buck converter in CCM is a function of the input and the output voltage. This relationship is written by Equation 2:
+
+**(EQ. 2)**
+
+$$D = \frac{V_{OUT}}{V_{IN}}$$
+
+Use Equation 3 to calculate the output inductor peak-to-peak ripple current:
+
+**(EQ. 3)**
+
+$$I_{P\text{-}P} = \frac{V_{OUT} \bullet (1 - D)}{f_{SW} \bullet L}$$
+
+A typical step-down DC/DC converter has an I<sub>P-P</sub> of 20% to 40% of the maximum DC output load current for a practical design. The value of I<sub>P-P</sub> is selected based on several criteria such as MOSFET switching loss, inductor core loss, and the resistive loss of the inductor winding.
+
+Use Equation 4 to estimate the DC copper loss of the inductor, where I<sub>LOAD</sub> is the converter output DC current.
+
+**(EQ. 4)**
+
+$$P_{COPPER} = I_{LOAD}{}^{2} \bullet DCR$$
+
+The copper loss can be significant, so select DCR carefully. Another factor to consider when choosing the inductor is its saturation characteristics at elevated temperatures. A saturated inductor can destroy circuit components.
+
+A DC/DC buck regulator must have output capacitance C<sub>O</sub> into which ripple current I<sub>P-P</sub> can flow. Current I<sub>P-P</sub> develops a corresponding ripple voltage V<sub>P-P</sub> across C<sub>O,</sub> which is the sum of the voltage drop across the capacitor ESR and of the voltage change stemming from charge moved in and out of the capacitor. Use Equation 5 and Equation 6 to calculate these two voltages:
+
+**(EQ. 5)**
+
+$$\Delta V_{ESR} = I_{P\text{-}P} \bullet ESR$$
+
+**(EQ. 6)**
+
+$$\Delta V_{C} = \frac{I_{P\text{-}P}}{8 \bullet C_{O} \bullet f_{SW}}$$
+
+If the output of the converter has to support a load with high pulsating current, several capacitors need to be paralleled to reduce the total ESR until the required V<sub>P-P</sub> is achieved. The inductance of the capacitor can cause a brief voltage dip if the load transient has an extremely high slew rate. Low inductance capacitors should be considered in this scenario. A capacitor dissipates heat as a function of RMS current and frequency. Ensure that I<sub>P-P</sub> is shared by a sufficient quantity of paralleled capacitors so that they operate below the maximum rated RMS current at f<sub>SW</sub>. Take into account that the rated value of a capacitor can fade as much as 50% as the DC voltage across it increases.
+
+<!-- page 62 -->
+
+## 9.2 Selecting the Input Capacitor
+
+The important parameters for input capacitance are the voltage rating and the RMS current rating. For reliable operation, select capacitors with voltage and current ratings above the maximum input voltage and that are capable of supplying the RMS current required by the switching circuit. Their voltage rating should be at least 1.25x greater than the maximum input voltage, while a voltage rating of 1.5x is a preferred rating. Figure 48 is a graph of the input capacitor RMS ripple current that is normalized relative to output load current. The graph is also a function of duty cycle and is adjusted for converter efficiency.
+
+**Figure 48. Normalized RMS Input Current at EFF = 1**
+
+![Figure 48. Normalized RMS Input Current at EFF = 1](09-general-application-information/figure-48.png)
+
+Use Equation 7 to calculate the normalized RMS ripple current calculation:
+
+**(EQ. 7)**
+
+$$I_{C_{IN}(RMS,NORMALIZED)} = \frac{I_{MAX} \cdot \sqrt{D \cdot (1 - D) + \dfrac{D \cdot k^{2}}{12}}}{I_{MAX}}$$
+
+where:
+
+- I<sub>MAX</sub> is the maximum continuous I<sub>LOAD</sub> of the converter
+- k is a multiplier (0 to 1) corresponding to the inductor peak-to peak ripple amplitude expressed as a ratio of I<sub>MAX</sub> (0 to 1)
+- D is the duty cycle that is adjusted to take into account the efficiency of the converter, which is calculated using Equation 8:
+
+**(EQ. 8)**
+
+$$D = \frac{V_{OUT}}{V_{IN} \cdot EFF}$$
+
+In addition to the capacitance, some low ESL ceramic capacitance is recommended to decouple between the drain of the high-side MOSFET and the source of the low-side MOSFET.
+
+## 9.3 Selecting the Switching Power MOSFET
+
+Typically, a MOSFET cannot tolerate even brief excursions beyond its maximum drain-to-source voltage rating. The MOSFETs used in the power stage of the converter should have a maximum VDS rating that exceeds both the sum of the upper voltage tolerance of the input power source and the voltage spike that occurs when the MOSFET switches off.
+
+Several power MOSFETs that are optimized for DC/DC converter applications are readily available. The preferred high-side MOSFET emphasizes low gate charge so that the device spends the least amount of time dissipating power in the linear region. Unlike the low-side MOSFET, which has the drain-to-source voltage clamped by its body diode during turn off, the high-side MOSFET turns off with a VDS of approximately VIN - VOUT, plus the
+
+<!-- page 63 -->
+
+spike across it. The preferred low-side MOSFET emphasizes low r<sub>DS(ON)</sub> when fully saturated to minimize conduction loss. *Note:* This is an optimal configuration of MOSFET selection for low duty cycle applications (D < 50%). For higher output, low input voltage solutions, a more balanced MOSFET selection for high-side and low-side devices might be required.
+
+The power loss of the Low-Side (LS) MOSFET can be assumed to be conductive only and is calculated using Equation 9:
+
+**(EQ. 9)**
+
+$$P_{CON\_LS} \approx I_{LOAD}{}^{2} \cdot r_{DS(ON)\_LS} \bullet (1 - D)$$
+
+Use Equation 10 to calculate the conduction loss of the High-Side (HS) MOSFET:
+
+**(EQ. 10)**
+
+$$P_{CON\_HS} = I_{LOAD}{}^{2} \bullet r_{DS(ON)\_HS} \bullet D$$
+
+Use Equation 11 to calculate the switching loss of the HS MOSFET:
+
+**(EQ. 11)**
+
+$$P_{SW\_HS} = \frac{V_{IN} \bullet I_{VALLEY} \bullet t_{SWON} \bullet f_{SW}}{2} + \frac{V_{IN} \bullet I_{PEAK} \bullet t_{SWOFF} \bullet f_{SW}}{2}$$
+
+where:
+
+- I<sub>VALLEY</sub> is the difference of the DC component of the inductor current minus 1/2 of the inductor ripple current
+- I<sub>PEAK</sub> is the sum of the DC component of the inductor current plus 1/2 of the inductor ripple current
+- t<sub>SW(ON)</sub> is the time required to drive the device into saturation
+- t<sub>SW(OFF)</sub> is the time required to drive the device into cut-off
+
+## 9.4 Selecting the Bootstrap Capacitor
+
+The selection of the bootstrap capacitor is written by Equation 12:
+
+**(EQ. 12)**
+
+$$C_{BOOT} = \frac{Q_{g}}{\Delta V_{BOOT}}$$
+
+where:
+
+- Q<sub>g</sub> is the total gate charge required to turn on the high-side MOSFET
+- ∆V<sub>BOOT</sub> is the maximum allowed voltage decay across the boot capacitor each time the high-side MOSFET is switched on.
+
+As an example, suppose the HS MOSFET has a total gate charge Q<sub>g</sub>, of 25nC at V<sub>GS</sub> = 5V and a ∆V<sub>BOOT</sub> of 200mV. The calculated bootstrap capacitance is 0.125µF; for a comfortable margin, select a capacitor that is double the calculated capacitance. In this example, 0.22µF is sufficient. Use an X7R or X5R ceramic capacitor. Renesas recommends using a bootstrap capacitor of 0.47µF (25V), which has an effective capacitance higher than 0.25µF at 5V and x50 effective high-side MOSFET gate capacitance.
+
+## 9.5 Switching Power MOSFET Gate Capacitance
+
+The RAA489118 includes an internal 5V LDO output at the `VDD` pin, which can be used to provide the switching MOSFET gate driver power through the `VDDP` pin with an RC filter. The 5V LDO output overcurrent protection threshold is 85mA, minimal (check EC table for the accurate value). When selecting the switching power MOSFET, consider the MOSFET gate capacitance carefully to avoid overloading the 5V LDO, especially in Buck-Boost mode when four MOSFETs are switching at the same time. For one MOSFET, use Equation 13 to estimate the gate drive current:
+
+**(EQ. 13)**
+
+$$I_{driver} = Q_{g} \bullet f_{SW}$$
+
+<!-- page 64 -->
+
+where:
+
+- Q<sub>g</sub> is the total gate charge, which can be found in the MOSFET datasheet
+- f<sub>SW</sub> is the switching frequency
+
+Renesas recommends using a 2.2µF (10V) `VDD`/`VDDP` capacitor, which has an effective capacitance higher than 0.4µF at 5V and x1.6 effective capacitance at the `BOOT` pin at 5V.
+
+## 9.6 DCIN Filter
+
+An RC filter is connected at the `DCIN` pin. Renesas recommends connecting a 10Ω `DCIN` resistor between the `DCIN` pin and the `VADP`/`VSYS` diodes, and connecting a 4.7µF `DCIN` capacitor to `GND`, which has an effective capacitance higher than 0.4µF at 28V.
+
+## 9.7 Adapter Input Filter
+
+The adapter cable parasitic inductance and capacitance can cause some voltage ringing or an overshoot spike at the adapter connector node when the adapter is hot plugged in. This voltage spike can damage the `ASGATE` MOSFET or the RAA489118 pins connecting to the adapter connector node. One low cost solution is to add an R-C snubber circuit at the adapter connector node to clamp the voltage spike as shown in Figure 49. A practical value of the R-C snubber is 2.2Ω to 2.2µF, while the appropriate values and power rating should be carefully characterized based on the actual design. Renesas does not recommend adding a pure capacitor at the adapter connector node, which can cause an even larger voltage spike due to the adapter cable or the adapter current path parasitic inductance.
+
+**Figure 49. Adapter Input R-C Snubber Circuit**
+
+![Figure 49. Adapter Input R-C Snubber Circuit](09-general-application-information/figure-49.png)

REN_RAA489118/10-layout.md

@@ -0,0 +1,43 @@
+<!-- page 65 -->
+
+# 10. Layout
+
+| Pin Number | Pin Name | Layout Guidelines |
+| --- | --- | --- |
+| Bottom Pad 33 | `GND` | Connect this ground pad to the ground plane through a low impedance path. Use at least five vias to connect to the PCB ground planes to ensure sufficient thermal dissipation directly under the IC. |
+| 1<br>2 | `CSON`<br>`CSOP` | Run two dedicated traces with sufficient width in parallel (close to each other to minimize the loop area) from the two terminals of the battery current sensing resistor to the IC. Place the differential mode and common-mode RC filter components in the general proximity of the controller.<br><br>Route the current sensing traces through vias to connect the center of the pads; or route the traces into the pads from the inside of the current sensing resistor. The following drawings show the two preferred ways of routing current sensing traces.<br><br>![Battery current sensing trace routing (uncaptioned drawing in the printed table cell)](10-layout/battery-current-sensing-trace-routing.png) |
+| 3 | `VSYS` | This signal pin provides feedback for the system bus voltage. Place the optional RC filter in the general proximity of the controller. Run a dedicated trace from the system bus to the pin and do not route near the switching traces. Do not share the same trace with the signal routing to the `DCIN` pin OR diodes and the `CSOP` trace. |
+| 4 | `BOOT2` | Switching pin. Place the bootstrap capacitor in the general proximity of the controller. Use sufficiently wide traces. Avoid any sensitive analog signal traces from crossing over or getting close. |
+| 5<br>6 | `UGATE2`<br>`PHASE2` | Run these two traces in parallel fashion with sufficient width. Avoid any sensitive analog signal traces from crossing over or getting close. Route the `PHASE2` trace to the high-side MOSFET source pin instead of general copper.<br><br>Place the IC close to the gate terminals of the switching MOSFETs and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the opposite side of the switching MOSFETs.<br><br>Place the output capacitors as close as possible to the switching high-side MOSFET drain and the low-side MOSFET source, and use shortest PCB trace connection. Place these capacitors on the same PCB layer with the MOSFETs instead of on different layers and using vias to make the connection.<br><br>Place the inductor terminal to the switching high-side MOSFET source and low-side MOSFET drain terminal as close as possible. Minimize this phase node area to lower the electrical and magnetic field radiation but make this phase node area large enough to carry the current. Place the inductor and the switching MOSFETs on the same layer of the PCB. |
+| 7 | `LGATE2` | Switching pin. Run the `LGATE2` trace in parallel with the `UGATE2` and `PHASE2` traces on the same PCB layer. Use sufficient width. Avoid any sensitive analog signal traces from crossing over or getting close. |
+| 8 | `VDDP` | Place the decoupling capacitor in the general proximity of the controller. Run the trace connecting to the `VDD` pin with sufficient width. |
+| 9 | `LGATE1` | Switching pin. Run the `LGATE1` trace in parallel with the `UGATE1` and `PHASE1` traces on the same PCB layer. Use sufficient width. Avoid any sensitive analog signal traces from crossing over or getting close. |
+
+<!-- page 66 -->
+
+| Pin Number | Pin Name | Layout Guidelines |
+| --- | --- | --- |
+| 10<br>11 | `PHASE1`<br>`UGATE1` | Run these two traces in parallel fashion with sufficient width. Avoid any sensitive analog signal traces from crossing over or getting close. Route the `PHASE1` trace to the high-side MOSFET source pin instead of general copper.<br><br>Place the IC close to the gate terminals of the switching MOSFETs and keep the gate drive signal traces short for a clean MOSFET drive. The IC can be placed on the opposite side of the switching MOSFETs.<br><br>Place the input capacitors as close as possible to the switching high-side MOSFET drain and the low-side MOSFET source, and use shortest PCB trace connection. Place these capacitors on the same PCB layer with the MOSFETs instead of on different layers and using vias to make the connection.<br><br>Place the inductor terminal to the switching high-side MOSFET source and low-side MOSFET drain terminal as close as possible. Minimize this phase node area to lower the electrical and magnetic field radiation but make this phase node area big enough to carry the current. Place the inductor and the switching MOSFETs on the same layer of the PCB. |
+| 12 | `BOOT1` | Switching pin. Place the bootstrap capacitor in the general proximity of the controller. Use sufficient wide trace. Avoid any sensitive analog signal traces from crossing over or getting close. |
+| 13 | `ASGATE` | Run this trace with sufficient width in parallel fashion with the `ADP` pin trace. |
+| 14<br>15 | `CSIN`<br>`CSIP` | Run two dedicated traces with sufficient width in parallel (close to each other to minimize the loop area) from the two terminals of the adapter current sensing resistor to the IC. Place the Differential mode and common-mode RC filter components in the general proximity of the controller.<br><br>Route the current sensing traces through vias to connect the center of the pads or route the traces into the pads from the inside of the current sensing resistor. The following drawings show the two preferred ways of routing current sensing traces.<br><br>![Adapter current sensing trace routing (uncaptioned drawing in the printed table cell)](10-layout/adapter-current-sensing-trace-routing.png) |
+| 16 | `ADP` | Run this trace with sufficient width in parallel fashion with the `ASGATE` pin trace. |
+| 17 | `DCIN` | Place the OR diodes and the RC filter in the general proximity of the controller. Run the `VADP` trace and `VSYS` trace to the OR diodes with sufficient width. |
+| 18 | `VDD` | Place the RC filter connecting with the `VDDP` pin in the general proximity of the controller. Run the trace connecting to the `VDDP` pin with sufficient width. |
+| 19 | `ACIN` | Place the voltage divider resistors and the optional decoupling capacitor in the general proximity of the controller. |
+| 20 | `OTGEN/CMIN` | No special consideration. |
+| 21<br>22 | `SDA`<br>`SCL` | Digital pins. No special consideration. Run the `SDA` and `SCL` traces in parallel. |
+| 23<br>24 | `PROCHOT#`<br>`ACOK` | Digital pin, open-drain output. No special consideration. |
+| 25 | `BATGONE` | Digital pin. Place the 100kΩ resistor series in the `BATGONE` signal trace and the optional decoupling capacitor in the general proximity of the controller. |
+
+<!-- page 67 -->
+
+| Pin Number | Pin Name | Layout Guidelines |
+| --- | --- | --- |
+| 26 | `OTGPG/CMOUT` | Digital pin, open-drain output. No special consideration. |
+| 27 | `PROG` | Signal pin. Place the `PROG` programming resistor in the general proximity of the controller. |
+| 28 | `COMP` | Place the compensation components in the general proximity of the controller. Avoid any switching signal from crossing over or getting close. |
+| 29 | `AMON/BMON` | No special consideration. Place the optional RC filter in the general proximity of the controller. |
+| 30 | `CONFIG/PSYS` | Dual-purpose pin: Configuration input or current source signal output. No special consideration. |
+| 31 | `VBAT` | Place the optional R-C filter in the general proximity of the controller. Run a dedicated trace from the battery positive connection point to the IC. |
+| 32 | `BGATE` | Use sufficient width trace from the IC to the `BGATE` MOSFET gate. Place the capacitor from `BGATE` to ground close to the MOSFET. |

REN_RAA489118/11-13-package-ordering-revision.md

@@ -0,0 +1,32 @@
+<!-- page 68 -->
+
+# 11. Package Outline Drawing
+
+The package outline drawing is located at the end of this document and is accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document.
+
+# 12. Ordering Information
+
+| Part Number[1][2] | Part Marking | Package Description[3]<br>(RoHS Compliant) | Pkg. Dwg # | Carrier Type[4] | Temp. Range |
+| --- | --- | --- | --- | --- | --- |
+| RAA489118ARGNP#AA0 | 489118 ARGNPA | 32 Ld 4x4 TQFN | L32.4x4D | Tray | -10 to +100°C |
+| RAA489118ARGNP#HA0 | 489118 ARGNPA | 32 Ld 4x4 TQFN | L32.4x4D | Reel, 6k | -10 to +100°C |
+| RAA489118A3GNP#AA0 | 489118 A3GNPA | 32 Ld 4x4 TQFN | L32.4x4D | Tray | -40 to +105°C |
+| RAA489118A3GNP#HA0 | 489118 A3GNPA | 32 Ld 4x4 TQFN | L32.4x4D | Reel, 6k | -40 to +105°C |
+| RAA489118A3GNP#MA0 | 489118 A3GNPA | 32 Ld 4x4 TQFN | L32.4x4D | Reel, 1k | -40 to +105°C |
+| RTKA489118DE0000BU | RAA489118 Evaluation Board - No BFET | | | | |
+| RTKA489118DE0010BU | RAA489118 Evaluation Board - with BFET | | | | |
+
+1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020.
+2. For the Moisture Sensitivity Level (MSL) see the RAA489118 product page. For more information about MSL, see TB363.
+3. For the Pb-Free Reflow Profile, see TB493.
+4. See TB347 for details about reel specifications.
+
+# 13. Revision History
+
+| Revision | Date | Description |
+| --- | --- | --- |
+| 2.00 | Oct 28, 2025 | In section 3.3 Thermal Specifications, updated the values for the Thermal Resistance parameter. |
+| 1.03 | Aug 21, 2025 | Updated the waveforms in Figures 10, 11, 21, and 22.<br>Updated Operation Mode values in Figure 39.<br>Updated POD L32.4x4D to the latest version. |
+| 1.02 | Jan 17, 2025 | Added RAA489118A3GNP#MA0 to the Ordering Information and the PCB ECAD Design Information. |
+| 1.01 | Oct 24, 2024 | Updated POD L32.4x4D to the latest version.<br>Added PCB ECAD Design Information. |
+| 1.00 | Aug 9, 2024 | Initial release |

REN_RAA489118/A-ecad-design-information.md

@@ -0,0 +1,128 @@
+<!-- page 69 -->
+
+# A. ECAD Design Information
+
+This information supports the development of the PCB ECAD model for this device. It is intended to be used by PCB designers.
+
+## A.1 Part Number Indexing
+
+| Orderable Part Number | Number of Pins | Package Type | Package Code/POD Number |
+| --- | --- | --- | --- |
+| RAA489118ARGNP#AA0 | 32 | TQFN | L32.4x4D |
+| RAA489118ARGNP#HA0 | 32 | TQFN | L32.4x4D |
+| RAA489118A3GNP#AA0 | 32 | TQFN | L32.4x4D |
+| RAA489118A3GNP#HA0 | 32 | TQFN | L32.4x4D |
+| RAA489118A3GNP#MA0 | 32 | TQFN | L32.4x4D |
+
+## A.2 Symbol Pin Information
+
+### A.2.1 32-TQFN
+
+| Pin Number | Primary Pin Name | Primary Electrical Type | Alternate Pin Name(s) |
+| --- | --- | --- | --- |
+| 1 | `CSON` | Input | - |
+| 2 | `CSOP` | Input | - |
+| 3 | `VSYS` | Input | - |
+| 4 | `BOOT2` | Power | - |
+| 5 | `UGATE2` | Output | - |
+| 6 | `PHASE2` | Power | - |
+| 7 | `LGATE2` | Output | - |
+| 8 | `VDDP` | Power | - |
+| 9 | `LGATE1` | Output | - |
+| 10 | `PHASE1` | Power | - |
+| 11 | `UGATE1` | Output | - |
+| 12 | `BOOT1` | Power | - |
+| 13 | `ASGATE` | Output | - |
+| 14 | `CSIN` | Input | - |
+| 15 | `CSIP` | Input | - |
+| 16 | `ADP` | Input | - |
+| 17 | `DCIN` | Power | - |
+| 18 | `VDD` | Power | - |
+| 19 | `ACIN` | Input | - |
+| 20 | `OTGEN` | Input | `CMIN` |
+| 21 | `SDA` | I/O | - |
+| 22 | `SCL` | I/O | - |
+| 23 | `PROCHOT#` | Output | - |
+| 24 | `ACOK` | Output | - |
+| 25 | `BATGONE` | Input | - |
+| 26 | `OTGPG` | Output | `CMOUT` |
+| 27 | `PROG` | Input | - |
+| 28 | `COMP` | Output | - |
+| 29 | `AMON` | Output | `BMON` |
+| 30 | `CONFIG` | I/O | `PSYS` |
+| 31 | `VBAT` | Input | - |
+
+<!-- page 70 -->
+
+| Pin Number | Primary Pin Name | Primary Electrical Type | Alternate Pin Name(s) |
+| --- | --- | --- | --- |
+| 32 | `BGATE` | Output | - |
+| EPAD33 | `GND` | Power | - |
+
+<!-- page 71 -->
+
+## A.3 Symbol Parameters
+
+| Orderable Part Number | Qualification | Mounting Type | Min Input Voltage | Max Input Voltage | Min Output Voltage | Max Output Voltage | Min Operating Temperature | Max Operating Temperature | RoHS | Trickle Charging | Typ Switching Frequency | Switcher Configuration |
+| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+| RAA489118ARGNP#AA0 | Consumer | SMD | 3.9 V | 30 V | 2.4 V | 30.8 V | -10° C | +100° C | Yes | Yes | 732 KHz | Buck, Boost, and Buck-Boost |
+| RAA489118ARGNP#HA0 | Consumer | SMD | 3.9 V | 30 V | 2.4 V | 30.8 V | -10° C | +100° C | Yes | Yes | 732 KHz | Buck, Boost, and Buck-Boost |
+| RAA489118A3GNP#AA0 | Industrial | SMD | 3.9 V | 30 V | 2.4 V | 30.8 V | -40° C | +105° C | Yes | Yes | 732 KHz | Buck, Boost, and Buck-Boost |
+| RAA489118A3GNP#HA0 | Industrial | SMD | 3.9 V | 30 V | 2.4 V | 30.8 V | -40° C | +105° C | Yes | Yes | 732 KHz | Buck, Boost, and Buck-Boost |
+| RAA489118A3GNP#MA0 | Industrial | SMD | 3.9 V | 30 V | 2.4 V | 30.8 V | -40° C | +105° C | Yes | Yes | 732 KHz | Buck, Boost, and Buck-Boost |
+
+<!-- page 72 -->
+
+## A.4 Footprint Design Information
+
+### A.4.1 32-TQFN
+
+| IPC Footprint Type | Package Code/ POD number | Number of Pins |
+| --- | --- | --- |
+| QFN | L32.4x4D | 32 |
+
+| Description | Dimension | Value (mm) | Diagram |
+| --- | --- | --- | --- |
+| Minimum body span (vertical side) | `Dmin` | 3.95 | |
+| Maximum body span (vertical side) | `Dmax` | 4.05 | |
+| Minimum body span (horizontal side) | `Emin` | 3.95 | |
+| Maximum body span (horizontal side) | `Emax` | 4.05 | |
+| Minimum Lead Width | `Bmin` | 0.15 | |
+| Maximum Lead Width | `Bmax` | 0.25 | |
+| Minimum Lead Length | `Lmin` | 0.25 | |
+| Maximum Lead Length | `Lmax` | 0.35 | |
+| Maximum Height | `Amax` | 0.8 | |
+| Minimum Standoff Height | `A1min` | 0 | |
+| Minimum Lead Thickness | `cmin` | 0.15 | |
+| Maximum Lead Thickness | `cmax` | 0.25 | |
+| Number of pins (vertical side) | `PinCountD` | 8 | |
+| Number of pins (horizontal side) | `PinCountE` | 8 | |
+| Distance between the center of any two adjacent pins (vertical side) | `PitchD` | 0.4 | |
+| Distance between the center of any two adjacent pins (horizontal side) | `PitchE` | 0.4 | |
+| Location of pin 1; S2 = corner of D side, C1 = center of E side | `Pin1` | S2 | |
+| Minimum thermal pad size (vertical side) | `D2min` | 2.6 | |
+| Maximum thermal pad size (vertical side) | `D2max` | 2.8 | |
+| Minimum thermal pad size (horizontal side) | `E2min` | 2.6 | |
+| Maximum thermal pad size (horizontal side) | `E2max` | 2.8 | |
+
+The "Diagram" column of the table above is a single cell spanning every row. It
+holds the following drawings, which carry no printed figure number and no
+printed caption:
+
+![Footprint dimensions diagram (uncaptioned drawing in the printed "Diagram" cell)](A-ecad-design-information/footprint-dimensions-diagram.png)
+
+| Recommended Land Pattern | Recommended Land Pattern | Recommended Land Pattern | Recommended Land Pattern |
+| --- | --- | --- | --- |
+| Description | Dimension | Value (mm) | Diagram |
+| Distance between left pad toe to right pad toe (horizontal side) | `ZE` | 4.4 | |
+| Distance between top pad toe to bottom pad toe (vertical side) | `ZD` | 4.4 | |
+| Distance between left pad heel to right pad heel (horizontal side) | `GE` | 3.4 | |
+| Distance between top pad heel to bottom pad heel (vertical side) | `GD` | 3.4 | |
+| Pad Width | `X` | 0.2 | |
+| Pad Length | `Y` | 0.5 | |
+
+The "Diagram" column of the Recommended Land Pattern table is a single cell
+spanning every row. It holds the following drawing, which carries no printed
+figure number and no printed caption:
+
+![Recommended land pattern diagram (uncaptioned drawing in the printed "Diagram" cell)](A-ecad-design-information/recommended-land-pattern-diagram.png)

REN_RAA489118/TOC.md

@@ -0,0 +1,262 @@
+# RAA489118 Datasheet — Table of Contents
+
+Markdown transcription of `REN_RAA489118_DST_20251028.pdf` (Renesas RAA489118
+Buck-Boost Battery Charger with SMBus Interface for General 30V and USB PD EPR),
+Rev.2.00, Oct 28 2025, document `R16DS0321EU0200`.
+
+The datasheet was split into the per-chapter PDFs in this folder; each has a
+matching `.md` transcription and, where the chapter contains figures, a folder
+of extracted PNGs. Page numbers below are the printed datasheet pages, and are
+mirrored in the transcriptions as `<!-- page N -->` markers.
+
+Not transcribed: the printed Contents pages (source pages 2–3), which this file
+replaces, and the closing Important Notice and Disclaimer (source pages 73–74).
+
+## Chapters
+
+| # | Chapter | Pages | Source PDF | Figures |
+|---|---|---|---|---|
+| — | [Features and Applications](00-features-applications.md) | 1 | [pdf](00-features-applications.pdf) | 1 |
+| 1 | [Overview](01-overview.md) | 4–6 | [pdf](01-overview.pdf) | 3 |
+| 2 | [Pin Information](02-pin-information.md) | 7–9 | [pdf](02-pin-information.pdf) | 1 |
+| 3 | [Specifications](03-specifications.md) | 10–20 | [pdf](03-specifications.pdf) | 1 |
+| 4 | [Typical Performance Graphs](04-typical-performance-graphs.md) | 21–25 | [pdf](04-typical-performance-graphs.pdf) | 26 |
+| 5 | [General SMBus Architecture](05-general-smbus-architecture.md) | 26–28 | [pdf](05-general-smbus-architecture.pdf) | 5 |
+| 6 | [Registers](06-registers.md) | 29–43 | [pdf](06-registers.pdf) | — |
+| 7 | [Modulator Information](07-modulator-information.md) | 44–51 | [pdf](07-modulator-information.pdf) | 8 |
+| 8 | [Application Information](08-application-information.md) | 52–60 | [pdf](08-application-information.pdf) | 2 |
+| 9 | [General Application Information](09-general-application-information.md) | 61–64 | [pdf](09-general-application-information.pdf) | 2 |
+| 10 | [Layout](10-layout.md) | 65–67 | [pdf](10-layout.pdf) | 2 |
+| 11–13 | [Package, Ordering, Revision History](11-13-package-ordering-revision.md) | 68 | [pdf](11-13-package-ordering-revision.pdf) | — |
+| A | [ECAD Design Information](A-ecad-design-information.md) | 69–72 | [pdf](A-ecad-design-information.pdf) | 2 |
+
+## Sections
+
+- [RAA489118](00-features-applications.md#raa489118)
+  - [Features](00-features-applications.md#features)
+  - [Applications](00-features-applications.md#applications)
+- [1. Overview](01-overview.md#1-overview)
+  - [1.1 Typical Application Diagram](01-overview.md#11-typical-application-diagram)
+  - [1.2 Block Diagram](01-overview.md#12-block-diagram)
+- [2. Pin Information](02-pin-information.md#2-pin-information)
+  - [2.1 Pin Assignments](02-pin-information.md#21-pin-assignments)
+  - [2.2 Pin Descriptions](02-pin-information.md#22-pin-descriptions)
+- [3. Specifications](03-specifications.md#3-specifications)
+  - [3.1 Absolute Maximum Ratings](03-specifications.md#31-absolute-maximum-ratings)
+  - [3.2 Recommended Operating Conditions](03-specifications.md#32-recommended-operating-conditions)
+  - [3.3 Thermal Specifications](03-specifications.md#33-thermal-specifications)
+  - [3.4 Electrical Specifications](03-specifications.md#34-electrical-specifications)
+  - [3.5 SMBus Timing Specification](03-specifications.md#35-smbus-timing-specification)
+  - [3.6 Gate Driver Timing Diagrams](03-specifications.md#36-gate-driver-timing-diagrams)
+- [4. Typical Performance Graphs](04-typical-performance-graphs.md#4-typical-performance-graphs)
+  - [4.1 Battery Charging Only (No BFET)](04-typical-performance-graphs.md#41-battery-charging-only-no-bfet)
+  - [4.2 NVDC Charging (with BFET)](04-typical-performance-graphs.md#42-nvdc-charging-with-bfet)
+- [5. General SMBus Architecture](05-general-smbus-architecture.md#5-general-smbus-architecture)
+  - [5.1 Data Validity](05-general-smbus-architecture.md#51-data-validity)
+  - [5.2 START and STOP Conditions](05-general-smbus-architecture.md#52-start-and-stop-conditions)
+  - [5.3 Acknowledge](05-general-smbus-architecture.md#53-acknowledge)
+  - [5.4 SMBus Transactions](05-general-smbus-architecture.md#54-smbus-transactions)
+  - [5.5 Byte Format](05-general-smbus-architecture.md#55-byte-format)
+  - [5.6 SMBus and I2C Compatibility](05-general-smbus-architecture.md#56-smbus-and-i2c-compatibility)
+  - [5.7 SMBus Commands](05-general-smbus-architecture.md#57-smbus-commands)
+- [6. Registers](06-registers.md#6-registers)
+  - [6.1 Register Summary](06-registers.md#61-register-summary)
+  - [6.2 DAC Register Summary](06-registers.md#62-dac-register-summary)
+  - [6.3 Control Registers](06-registers.md#63-control-registers)
+  - [6.4 Information Registers](06-registers.md#64-information-registers)
+- [7. Modulator Information](07-modulator-information.md#7-modulator-information)
+  - [7.1 RAA489118 Buck-Boost Charger Modes of Operation](07-modulator-information.md#71-raa489118-buck-boost-charger-modes-of-operation)
+  - [7.2 USB On-the-Go (USB OTG)](07-modulator-information.md#72-usb-on-the-go-usb-otg)
+  - [7.3 Pass-Through Mode](07-modulator-information.md#73-pass-through-mode)
+  - [7.4 Modulator Control Loops](07-modulator-information.md#74-modulator-control-loops)
+    - [7.4.1 Adapter Current Loop and Two-Level Current Limit](07-modulator-information.md#741-adapter-current-loop-and-two-level-current-limit)
+    - [7.4.2 USB-PD On-the-Go Output Current](07-modulator-information.md#742-usb-pd-on-the-go-output-current)
+    - [7.4.3 Input Voltage Regulation Loop](07-modulator-information.md#743-input-voltage-regulation-loop)
+      - [7.4.3.1 Adapter Minimum Voltage](07-modulator-information.md#7431-adapter-minimum-voltage)
+      - [7.4.3.2 USB-PD On-the-Go Minimum Battery Voltage](07-modulator-information.md#7432-usb-pd-on-the-go-minimum-battery-voltage)
+    - [7.4.4 USB-PD On-the-Go Output Voltage](07-modulator-information.md#744-usb-pd-on-the-go-output-voltage)
+    - [7.4.5 System Voltage Regulation and Trickle Charging](07-modulator-information.md#745-system-voltage-regulation-and-trickle-charging)
+    - [7.4.6 Charging Current Loop](07-modulator-information.md#746-charging-current-loop)
+      - [7.4.6.1 Reverse Mode Discharge Current](07-modulator-information.md#7461-reverse-mode-discharge-current)
+    - [7.4.7 Turbo Mode Support](07-modulator-information.md#747-turbo-mode-support)
+  - [7.5 R3 Modulator](07-modulator-information.md#75-r3-modulator)
+- [8. Application Information](08-application-information.md#8-application-information)
+  - [8.1 Soft-Start](08-application-information.md#81-soft-start)
+  - [8.2 Charging Mode Configuration](08-application-information.md#82-charging-mode-configuration)
+    - [8.2.1 Battery Charging Only (no BFET)](08-application-information.md#821-battery-charging-only-no-bfet)
+    - [8.2.2 NVDC Charging (with BFET)](08-application-information.md#822-nvdc-charging-with-bfet)
+  - [8.3 Programming Charger Option](08-application-information.md#83-programming-charger-option)
+  - [8.4 Autonomous Charging Mode](08-application-information.md#84-autonomous-charging-mode)
+  - [8.5 Battery Ship Mode](08-application-information.md#85-battery-ship-mode)
+  - [8.6 Diode Emulation Operation](08-application-information.md#86-diode-emulation-operation)
+  - [8.7 Battery Learn Mode](08-application-information.md#87-battery-learn-mode)
+  - [8.8 Charger Timeout](08-application-information.md#88-charger-timeout)
+  - [8.9 Monitoring](08-application-information.md#89-monitoring)
+    - [8.9.1 Current Monitor](08-application-information.md#891-current-monitor)
+    - [8.9.2 PSYS Monitor](08-application-information.md#892-psys-monitor)
+    - [8.9.3 PROCHOT#](08-application-information.md#893-prochot)
+  - [8.10 Stand-Alone Comparator](08-application-information.md#810-stand-alone-comparator)
+  - [8.11 Protections[1]](08-application-information.md#811-protections1)
+    - [8.11.1 Adapter Overvoltage Protection](08-application-information.md#8111-adapter-overvoltage-protection)
+    - [8.11.2 System Overvoltage Protection](08-application-information.md#8112-system-overvoltage-protection)
+    - [8.11.3 System Voltage Rail Short Protection](08-application-information.md#8113-system-voltage-rail-short-protection)
+    - [8.11.4 System Voltage Undervoltage Protection (for Short-Circuit Protection)](08-application-information.md#8114-system-voltage-undervoltage-protection-for-short-circuit-protection)
+    - [8.11.5 Over-Temperature Protection](08-application-information.md#8115-over-temperature-protection)
+  - [8.12 Selecting the Power Source](08-application-information.md#812-selecting-the-power-source)
+- [9. General Application Information](09-general-application-information.md#9-general-application-information)
+  - [9.1 Selecting the LC Output Filter](09-general-application-information.md#91-selecting-the-lc-output-filter)
+  - [9.2 Selecting the Input Capacitor](09-general-application-information.md#92-selecting-the-input-capacitor)
+  - [9.3 Selecting the Switching Power MOSFET](09-general-application-information.md#93-selecting-the-switching-power-mosfet)
+  - [9.4 Selecting the Bootstrap Capacitor](09-general-application-information.md#94-selecting-the-bootstrap-capacitor)
+  - [9.5 Switching Power MOSFET Gate Capacitance](09-general-application-information.md#95-switching-power-mosfet-gate-capacitance)
+  - [9.6 DCIN Filter](09-general-application-information.md#96-dcin-filter)
+  - [9.7 Adapter Input Filter](09-general-application-information.md#97-adapter-input-filter)
+- [10. Layout](10-layout.md#10-layout)
+- [11. Package Outline Drawing](11-13-package-ordering-revision.md#11-package-outline-drawing)
+- [12. Ordering Information](11-13-package-ordering-revision.md#12-ordering-information)
+- [13. Revision History](11-13-package-ordering-revision.md#13-revision-history)
+- [A. ECAD Design Information](A-ecad-design-information.md#a-ecad-design-information)
+  - [A.1 Part Number Indexing](A-ecad-design-information.md#a1-part-number-indexing)
+  - [A.2 Symbol Pin Information](A-ecad-design-information.md#a2-symbol-pin-information)
+    - [A.2.1 32-TQFN](A-ecad-design-information.md#a21-32-tqfn)
+  - [A.3 Symbol Parameters](A-ecad-design-information.md#a3-symbol-parameters)
+  - [A.4 Footprint Design Information](A-ecad-design-information.md#a4-footprint-design-information)
+    - [A.4.1 32-TQFN](A-ecad-design-information.md#a41-32-tqfn)
+
+## Figure index
+
+All 49 numbered figures, plus four drawings the datasheet prints with no number
+and no caption.
+
+| Figure | Image |
+|---|---|
+| Figure 1. Full-Featured Architecture Solutions Enabled by RAA489118 | 00-features-applications/figure-01.png |
+| Figure 2. Typical Application Circuit #1 (Battery Charging Only with No BFET) | 01-overview/figure-02.png |
+| Figure 3. Typical Application Circuit #2 (NVDC Charging with a BFET) | 01-overview/figure-03.png |
+| Figure 4. Block Diagram | 01-overview/figure-04.png |
+| Figure 5. Pin Assignments – Top View | 02-pin-information/figure-05.png |
+| Figure 6. Gate Driver Timing Diagram | 03-specifications/figure-06.png |
+| Figure 7. Adapter Insertion, VADP: 0V → 5V, VBAT = 18V, ChargeCurrent = 0.256A | 04-typical-performance-graphs/figure-07.png |
+| Figure 8. Adapter Insertion, VADP: 0V → 5V, VBAT = 18V, ChargeCurrent = 0.256A (Figure 7 Zoomed In) | 04-typical-performance-graphs/figure-08.png |
+| Figure 9. Adapter Removal, VADP: 28V → 0V, VBAT = 18V, ChargeCurrent = 6A | 04-typical-performance-graphs/figure-09.png |
+| Figure 10. Adapter Voltage Ramp Up, Boost → Buck-Boost → Buck Operation Mode Transitions | 04-typical-performance-graphs/figure-10.png |
+| Figure 11. Adapter Voltage Ramp Down, Buck → Buck-Boost → Boost Operation Mode Transitions | 04-typical-performance-graphs/figure-11.png |
+| Figure 12. Boost Mode: Charge Current Loop to Adapter Current Loop, VADP = 5V, VBAT = 16V, AdapterCurrentLimit = 3A, ChargeCurrent: 0.5A → 1A | 04-typical-performance-graphs/figure-12.png |
+| Figure 13. Buck_Boost Mode: Charge Current Loop to Adapter Current Loop, VADP = 20V, VBAT = 19V, AdapterCurrentLimit = 5A, ChargeCurrent: 2A → 6A Buck_Boost_CCM_stretch_period = 2x | 04-typical-performance-graphs/figure-13.png |
+| Figure 14. Buck Mode: Charge Current Loop to Adapter Current Loop, VADP = 28V, VBAT = 22V, AdapterCurrentLimit = 5A, ChargeCurrent: 1A → 7A | 04-typical-performance-graphs/figure-14.png |
+| Figure 15. Boost Mode: Charge Current Loop to Input Voltage Loop, VADP = 5V, VBAT = 16V, ChargeCurrent: 0.5A → 2A, InputVoltageLimit = 4.096V | 04-typical-performance-graphs/figure-15.png |
+| Figure 16. OTG Mode Enable, OTG_Debounce = 150ms, VBAT = 29.4V, VOTG = 20V | 04-typical-performance-graphs/figure-16.png |
+| Figure 17. OTG Mode Transients, VBAT = 29.4V, VOTG = 20V, OTG Load: 0.5A ↔ 3A | 04-typical-performance-graphs/figure-17.png |
+| Figure 18. Adapter Insertion, VADP: 0V → 5V, VBAT = 18V, ChargeCurrent = 0A | 04-typical-performance-graphs/figure-18.png |
+| Figure 19. Adapter Insertion, VADP: 0V → 5V, VBAT = 18V, ChargeCurrent = 0A (Figure 18 Zoomed In) | 04-typical-performance-graphs/figure-19.png |
+| Figure 20. Adapter Removal, VADP: 28V → 0V, VBAT = 18V, SystemLoad = 2A | 04-typical-performance-graphs/figure-20.png |
+| Figure 21. Adapter Voltage Ramp Up, Boost → Buck-Boost → Buck Operation Mode Transitions | 04-typical-performance-graphs/figure-21.png |
+| Figure 22. Adapter Voltage Ramp Down, Buck → Buck-Boost → Boost Operation Mode Transitions | 04-typical-performance-graphs/figure-22.png |
+| Figure 23. Boost Mode: Output Voltage Loop ↔ Adapter Current Loop, VADP = 5V, MaxSystemVoltage = 21V, VBAT = 20.5V, AdapterCurrentLimit = 3A, ChargeCurrent = 0A, SystemLoad: 0.2A ↔ 4A | 04-typical-performance-graphs/figure-23.png |
+| Figure 24. Boost Mode: Charge Current Loop ↔ Adapter Current Loop, VADP = 5V, MaxSystemVoltage = 21V, VBAT = 16V, AdapterCurrentLimit = 3A, ChargeCurrent = 0.5A, SystemLoad: 0A ↔ 4A | 04-typical-performance-graphs/figure-24.png |
+| Figure 25. Buck-Boost Mode: Output Voltage Loop ↔ Adapter Current Loop, VADP = 20V, MaxSystemVoltage = 21V, VBAT = 20.5V, AdapterCurrentLimit = 5A, ChargeCurrent = 0A, SystemLoad: 2A ↔ 8A, Buck_Boost_CCM_stretch_period = 2x | 04-typical-performance-graphs/figure-25.png |
+| Figure 26. Buck-Boost Mode: Charge Current Loop ↔ Adapter Current Loop, VADP = 20V, MaxSystemVoltage = 21V, VBAT = 20V, AdapterCurrentLimit = 5A, ChargeCurrent = 1A, SystemLoad: 2A ↔ 8A, Buck_Boost_CCM_stretch_period = 2x | 04-typical-performance-graphs/figure-26.png |
+| Figure 27. Buck Mode: Output Voltage Loop ↔ Adapter Current Loop, VADP = 28V, MaxSystemVoltage = 21V, VBAT = 20.5V, AdapterCurrentLimit = 5A, ChargeCurrent = 0A, SystemLoad: 2A ↔ 12A | 04-typical-performance-graphs/figure-27.png |
+| Figure 28. Buck Mode: Charge Current Loop ↔ Adapter Current Loop, VADP = 28V, MaxSystemVoltage = 21V, VBAT = 20V, AdapterCurrentLimit = 5A, ChargeCurrent = 1A, SystemLoad: 2A ↔ 12A | 04-typical-performance-graphs/figure-28.png |
+| Figure 29. Boost Mode: Output Voltage Loop ↔ Input Voltage Loop, VADP = 5V, MaxSystemVoltage = 21V, VBAT = 20.5V, InputVoltageLimit = 4.096V, ChargeCurrent = 0A, SystemLoad: 0A ↔ 4A | 04-typical-performance-graphs/figure-29.png |
+| Figure 30. Boost Mode: Charge Current Loop ↔ Input Voltage Loop, VADP = 5V, MaxSysVoltage = 21V, VBAT = 16V, InputVoltageLimit = 4.096V, ChargeCurrent = 0.5A, SystemLoad: 0A ↔ 4A | 04-typical-performance-graphs/figure-30.png |
+| Figure 31. OTG Mode Enable. OTG_Debounce = 150ms, VBAT = 29.4V, VOTG = 20V | 04-typical-performance-graphs/figure-31.png |
+| Figure 32. OTG Mode Transients. VBAT = 29.4V, VOTG = 20V, OTG Current = 5A, OTG Load: 0.5A ↔ 3A | 04-typical-performance-graphs/figure-32.png |
+| Figure 33. General SMBus | 05-general-smbus-architecture/figure-33.png |
+| Figure 34. Data Validity | 05-general-smbus-architecture/figure-34.png |
+| Figure 35. Start and Stop Waveforms | 05-general-smbus-architecture/figure-35.png |
+| Figure 36. Acknowledge On The SMBus | 05-general-smbus-architecture/figure-36.png |
+| Figure 37. SMBus Read and Write Protocol | 05-general-smbus-architecture/figure-37.png |
+| Figure 38. Buck-Boost Charger Topology | 07-modulator-information/figure-38.png |
+| Figure 39. Operation Mode | 07-modulator-information/figure-39.png |
+| Figure 40. Charger Control Loops | 07-modulator-information/figure-40.png |
+| Figure 41. Two-Level Adapter Current Limit | 07-modulator-information/figure-41.png |
+| Figure 42. R3 Modulator | 07-modulator-information/figure-42.png |
+| Figure 43. R3 Modulator Operation Principles In Steady State | 07-modulator-information/figure-43.png |
+| Figure 44. R3 Modulator Operation Principles In Dynamic Response | 07-modulator-information/figure-44.png |
+| Figure 45. Diode Emulation | 07-modulator-information/figure-45.png |
+| Figure 46. Period Stretching | 08-application-information/figure-46.png |
+| Figure 47. PSYS Accuracy and Limits | 08-application-information/figure-47.png |
+| Figure 48. Normalized RMS Input Current at EFF = 1 | 09-general-application-information/figure-48.png |
+| Figure 49. Adapter Input R-C Snubber Circuit | 09-general-application-information/figure-49.png |
+| *(uncaptioned)* Battery current sensing trace routing, printed page 65 | 10-layout/battery-current-sensing-trace-routing.png |
+| *(uncaptioned)* Adapter current sensing trace routing, printed page 66 | 10-layout/adapter-current-sensing-trace-routing.png |
+| Footprint dimensions diagram (uncaptioned drawing in the printed "Diagram" cell) | A-ecad-design-information/footprint-dimensions-diagram.png |
+| Recommended land pattern diagram (uncaptioned drawing in the printed "Diagram" cell) | A-ecad-design-information/recommended-land-pattern-diagram.png |
+
+## Known defects in the source datasheet
+
+Each of these is printed exactly as shown in the PDF and is reproduced verbatim
+in the transcription. Do not "fix" them — every one was confirmed against the
+rendered page by an independent audit pass.
+
+| Printed page | What the datasheet prints | Why it looks wrong |
+|---|---|---|
+| 11–19 | `... VSYS = VBAT = CSOP = CSON = 8V and 29.4, unless otherwise noted.` | The Electrical Specifications conditions line omits the `V` unit after `29.4`. Repeated on every page of the table, while the test-condition cells in the same table do print `29.4V`. |
+| 27 | `See Table 1 for register details.` | Cross-reference from Section 5 to Table 1, which lives in Section 6. Correct under the datasheet's document-wide table numbering, dangling in a per-chapter split. |
+| 28 | `It responds to the 7-bit address 0b0001001_ as follows:` | Trailing underscore where the R/W bit placeholder should be. |
+| 28 | `Read address = 0b00010011 (0X13H)` and `Write address = 0b00010010 (0X12H)` | Capital `X` in the hex prefix plus a redundant trailing `H`. These are also 8-bit addresses, one sentence after being called a 7-bit address. |
+| 35 | `Control2 Bit[13] and Control 3 Bit[0] configures ...` | `Control 3` with a space, inconsistent with `Control3` everywhere else; singular verb with a compound subject. |
+| 36 | `Table 5. Control2 Register 0x3DH  (Cont.)` | Double space before `(Cont.)`; every other continuation caption uses one. |
+| 36, 37 | Table 6 column header `Description` with a superscript `7` | A footnote marker with no footnote 7 defined anywhere in the chapter. |
+| 37 | Lead-in reads `Control7[7] and Control3[8]`; the sub-table headers read `Control3 [8]` and `Control7 [7]` | Spaces before the bit brackets in the headers only. |
+| 40 | `Table 8. Control5 Register 0x38H` at the top of the page | Continuation caption missing `(Cont.)`, unlike Tables 5, 6 and 7. |
+| 42 | `Program Resister read out` | "Resister" for "Resistor". |
+| 45 | `BATGONE must be low to enable OTG mode.` | Printed twice in Section 7.2 — once ending the first paragraph and again as a standalone closing paragraph. |
+| 45 | `The OTG Voltage register 0x49h configure the OTG output voltage.` | Singular subject with plural verb, and a lowercase `h` hex suffix that the same section mixes with bare `0x49`. |
+| 54 | `... only configured if CONGIG/PSYS pin is pulled low at POR.` | `CONGIG` for `CONFIG`, in the first occurrence of the Table 16 footnote only; the second occurrence is spelled correctly. |
+| 54 | `MaxVsystemVoltage` | Inconsistent casing for `MaxSystemVoltage`. |
+| 55 | `Using this R1 = 10mΩ and Rs2 = 5mΩ` | `R1` where `Rs1` is meant. |
+| 56 | `... Control0 register Bit[7] as shown Table 3.` | Missing "in". |
+| 59 | `When the ADP voltage drops below 32.7V from more than 100µs, it starts to turn on ASGATE and start switching.` | "from" for "for", and a number-agreement slip on "start switching". |
+| 62 | `... corresponding to the inductor peak-to peak ripple amplitude ...` | Missing hyphen; page 61 spells it `peak-to-peak`. |
+| 63 | EQ. 11 prints `t_SWON` and `t_SWOFF`; its `where:` list prints `t_SW(ON)` and `t_SW(OFF)` | The same two symbols written two ways on one page. |
+| 61–64 | Equation numbering starts at `(EQ. 2)` | There is no `(EQ. 1)` in Section 9, and nothing appears to be missing. |
+| 69 vs 72 | `Package Code/POD Number` versus `Package Code/ POD number` | Spacing and casing differ between A.1 and A.4.1. |
+| 71 | `-10° C`, `+100° C`, `-40° C`, `+105° C` | Space between the degree sign and `C`. |
+| 71 | `732 KHz` | Capital `K`; should be `kHz`. |
+| 22, 24, 25 | Figure 13 says `Buck_Boost Mode` while Figures 25 and 26 say `Buck-Boost Mode`; Figure 30 says `MaxSysVoltage` while Figures 23–29 say `MaxSystemVoltage`; Figures 16 and 17 use a comma after the title where Figures 31 and 32 use a period | Caption style is inconsistent across the performance-graph chapter. |
+
+## Transcription notes
+
+- Figure captions are the printed caption text only. No figure is described in
+  prose; the extracted image carries that information.
+- Where the printed source merges cells vertically, the value is repeated on
+  every Markdown row, because GFM has no rowspan. Where a table is nested inside
+  a description cell, it is rendered as inline HTML so the outer table stays
+  intact.
+- Four drawings carry no printed figure number and no caption (printed pages 65,
+  66, and two on page 72). They were cropped by explicit region rather than
+  given invented numbers:
+
+```
+python3 tools/extract-figures.py \
+  --region '1:220,255,490,360:battery-current-sensing-trace-routing.png' \
+  --region '2:225,412,485,518:adapter-current-sensing-trace-routing.png' \
+  REN_RAA489118/10-layout.pdf
+
+python3 tools/extract-figures.py \
+  --region '4:385,172,544,465:footprint-dimensions-diagram.png' \
+  --region '4:385,533,544,688:recommended-land-pattern-diagram.png' \
+  REN_RAA489118/A-ecad-design-information.pdf
+```
+
+- Figures 1 and 38 were re-cropped explicitly as well. A two-column marketing
+  page and a table sitting directly above a drawing both defeat caption-anchored
+  band detection:
+
+```
+python3 tools/extract-figures.py \
+  --region '1:40,530,560,666:figure-01.png' \
+  REN_RAA489118/00-features-applications.pdf
+
+python3 tools/extract-figures.py \
+  --region '1:40,372,560,494:figure-38.png' \
+  REN_RAA489118/07-modulator-information.pdf
+```
+
+- Every other figure came from the caption-anchored pass:
+
+```
+python3 tools/extract-figures.py REN_RAA489118/*.pdf
+```