305 lines
30 KiB
Markdown
305 lines
30 KiB
Markdown
<!-- page 29 -->
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# 6. Registers
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The register descriptions below are based on current-sensing resistors R<sub>s1</sub> = 10mΩ and R<sub>s2</sub> = 5mΩ, unless otherwise specified.
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## 6.1 Register Summary
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**Table 1. Register Summary**
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| Register Names | Register Address | Read/ Write | Number of Bits | Description | Default |
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| --- | --- | --- | --- | --- | --- |
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| `ChargeCurrentLimit` | `0x14` | R/W | 11 | [12:2], LSB size 8mA | 256mA: `CONFIG` = VDD<br>0A: Otherwise |
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| `MaxSystemVoltage` | `0x15` | R/W | 12 | [14:3], LSB size 16mV | 8.4V<br>12.608V<br>16.8V<br>21.008V<br>25.2V<br>29.408V<br>(Set by `PROG` pin) |
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| `Control7` | `0x36` | R/W | 3 | [7], [1:0], configures various charger options | `0x0000` |
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| `Control6` | `0x37` | R/W | 8 | [7:0], configures various charger options | `0x0040` or `0x0043`[1] |
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| `Control5` | `0x38` | R/W | 16 | Configures various charger options | `0x0000` |
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| `Control0` | `0x39` | R/W | 16 | Configures various charger options | `0x0000` |
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| `Information1` | `0x3A` | R | 16 | Indicates various charger statuses | `0x0000` |
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| `AdapterCurrentLimit2` | `0x3B` | R/W | 11 | [12:2], LSB size 8mA | 1.504A |
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| `Control1` | `0x3C` | R/W | 16 | Configures various charger options | `0x0200` |
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| `Control2` | `0x3D` | R/W | 16 | Configures various charger options | `0x0000` |
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| `MinSystemVoltage` | `0x3E` | R/W | 8 | [13:6], LSB size 128mV | 5.12V<br>7.68V<br>10.24V<br>12.80V<br>15.36V<br>17.92V<br>(Set by `PROG` pin) |
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| `AdapterCurrentLimit1` | `0x3F` | R/W | 11 | [12:2], LSB size 8mA | 0.48A or 1.504A<br>(Set by `PROG` pin) |
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| Revision ID | `0x44` | R | 8 | Revision ID register - Read only | `0x00` |
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| `ACProchot#` | `0x47` | R/W | 6 | [12:7] Adapter current `PROCHOT#` threshold, 256mA resolution for 10mΩ R<sub>s1</sub>. | 3.072A |
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| `DCProchot#` | `0x48` | R/W | 6 | [13:8] Battery discharging current `PROCHOT#` threshold, 512mA resolution for 5mΩ R<sub>s2</sub>. | 4.096A |
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| OTG Voltage | `0x49` | R/W | 12 | [14:3], LSB size 18mV,<br>OTG mode voltage reference | 5.004V |
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| OTG Current | `0x4A` | R/W | 9 | [12:4], LSB size 32mA,<br>OTG mode maximum current limit | 0.512A |
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**Table 1. Register Summary (Cont.)**
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| Register Names | Register Address | Read/ Write | Number of Bits | Description | Default |
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| --- | --- | --- | --- | --- | --- |
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| V<sub>IN</sub> Voltage | `0x4B` | R/W | 6 | [13:8], LSB size 512mV,<br>V<sub>IN</sub> loop voltage reference | 4.096V |
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| `Control3` | `0x4C` | R/W | 16 | Configures various charger options | `0x0000` or `0x0080`[2] |
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| `Information2` | `0x4D` | R | 16 | Indicates various charger statuses | `0x0000` |
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| `Control4` | `0x4E` | R/W | 16 | Configures various charger options | `0x0000` |
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| `Information3` | `0x90` | R | 1 | [1] indicates pass-through mode status | `0x0000` |
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| Manufacturer ID | `0xFE` | R | 8 | Manufacturer ID register – `0x49` - Read only | `0x0049` |
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| Device ID | `0xFF` | R | 8 | Device ID register - Read only | `0x0018` |
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1. The default value for the VSYS UV field depends on the `CONFIG` pin state and whether powering up from battery.
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2. `Control3` Bit[7] is set by `PROG` pin, see Table 16.
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<!-- page 31 -->
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## 6.2 DAC Register Summary
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**Table 2. DAC Summary Table[1]**
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| ADDR Bit | Charge Current Limit (R<sub>s2</sub> = 5mΩ) | Max System Voltage | Min System Voltage | Adapter Current Limit1 (R<sub>s1</sub> = 10mΩ) | Adapter Current Limit2 (R<sub>s1</sub> = 10mΩ) | V<sub>IN</sub> Voltage (ADP Min Voltage or BAT Min Voltage) | ACProchot# (ACHOT) (R<sub>s1</sub> = 10mΩ) | DCProchot# (DCHOT) (R<sub>s2</sub> = 5mΩ) | OTG Voltage | OTG Current (R<sub>s1</sub> = 10mΩ) |
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| --- | --- | --- | --- | --- | --- | --- | --- | --- | --- | --- |
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| | `0x14` | `0x15` | `0x3E` | `0x3F` | `0x3B` | `0x4B` | `0x47` | `0x48` | `0x49` | `0x4A` |
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| `[0]` | - | - | - | - | - | - | - | - | - | - |
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| `[1]` | - | - | - | - | - | - | - | - | - | - |
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| `[2]` | 8mA | - | - | 8mA | 8mA | - | - | - | - | - |
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| `[3]` | 16mA | 16mV | - | 16mA | 16mA | - | - | - | 18mV | - |
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| `[4]` | 32mA | 32mV | - | 32mA | 32mA | - | - | - | 36mV | 32mA |
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| `[5]` | 64mA | 64mV | - | 64mA | 64mA | - | - | - | 72mV | 64mA |
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| `[6]` | 128mA | 128mV | 128mV | 128mA | 128mA | - | - | - | 144mV | 128mA |
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| `[7]` | 256mA | 256mV | 256mV | 256mA | 256mA | - | 256mA | - | 288mV | 256mA |
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| `[8]` | 512mA | 512mV | 512mV | 512mA | 512mA | 512mV | 512mA | 512mA | 576mV | 512mA |
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| `[9]` | 1024mA | 1024mV | 1024mV | 1024mA | 1024mA | 1024mV | 1024mA | 1024mA | 1152mV | 1024mA |
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| `[10]` | 2048mA | 2048mV | 2048mV | 2048mA | 2048mA | 2048mV | 2048mA | 2048mA | 2304mV | 2048mA |
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| `[11]` | 4096mA | 4096mV | 4096mV | 4096mA | 4096mA | 4096mV | 4096mA | 4096mA | 4608mV | 4096mA |
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| `[12]` | 8192mA | 8192mV | 8192mV | 8192mA | 8192mA | 8192mV | 8192mA | 8192mA | 9216mV | 8192mA |
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| `[13]` | - | 16384mV | 16384mV | - | - | 16384mV | - | 16384mA | 18432mV | - |
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| `[14]` | - | 0mV | - | - | - | - | - | - | 0mV | - |
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| `[15]` | - | - | - | - | - | - | - | - | - | - |
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| Max | 12.16A (`0x17C0`) | 32.256V (`0x3F00`) | 25.088V (`0x3100`) | 12.16A (`0x17C0`) | 12.16A (`0x17C0`) | 27.648A (`0x3600`) | 12.8A (`0x1900`) | 25.6A (`0x3200`) | 32.256V (`0x3800`) | 8.192A (`0x1000`) |
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| Default | CFG = VDD: 0.256A (`0x0080`)<br>CFG ≠ VDD: 0A (`0x0000`) | Set by `PROG` | Set by `PROG` | 0.48A (`0x00F0`) or 1.504A (`0x02F0`) (Set by `PROG`) | 1.504A (`0x02F0`) | 4.096V (`0x0800`) | 3.072A (`0x0600`) | 4.096A (`0x0800`) | 5.004V (`0x08B0`) | 0.512A (`0x0100`) |
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1. Each of the DAC registers accepts any value, but only the valid register bits are written to the register and the voltage or current value is clamped at the indicated maximum. The RAA489118 accepts a 0V command for the `MaxSystemVoltage` register, but the register value does not change. The `MinSystemVoltage` value should be lower than the `MaxSystemVoltage` value.
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## 6.3 Control Registers
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The Control registers configure the operation of the RAA489118. To change the configuration after a POR, write to the appropriate control registers using the Write-word protocol shown in Figure 37.
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**Table 3. Control0 Register 0x39H**
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| Bit | Bit Name | Description |
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| --- | --- | --- |
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| `[15:13]` | Forward Buck Phase Comparator Threshold Offset | Bit[15:13] adjusts the phase comparator threshold offset for the forward buck mode.<br>`000` = 0mV (default)<br>`001` = 1mV<br>`010` = 2mV<br>`011` = 3mV<br>`100` = -4mV<br>`101` = -3mV<br>`110` = -2mV<br>`111` = -1mV |
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| `[12:10]` | Forward Buck-boost, Forward Boost, and Reverse Boost Phase Comparator Threshold Offset | Bit[12:10] adjusts the phase comparator threshold offset for the forward buck-boost, forward boost, and reverse boost modes.<br>`000` = 0mV (default)<br>`001` = 0.5mV<br>`010` = 1mV<br>`011` = 1.5mV<br>`100` = -2mV<br>`101` = -1.5mV<br>`110` = -1mV<br>`111` = -0.5mV |
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| `[9,8,0]` | Reverse Buck and Reverse Buck-boost Phase Comparator Threshold Offset | Bit[9,8,0] adjusts the phase comparator threshold offset for the reverse buck and reverse buck-boost modes.<br>`000` = 0mV (default)<br>`001` = 1mV<br>`010` = 2mV<br>`011` = 3mV<br>`100` = -4mV<br>`101` = -3mV<br>`110` = -2mV<br>`111` = -1mV |
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| `[7]` | SMBus Timeout | Bit[7] enables or disables the charger timeout function in NVDC charging mode (`CONFIG` pulled low). If the adapter is present and the RAA489118 does not receive a write command to the `MaxSystemVoltage`(`0x15`) or `ChargeCurrentLimit`(`0x14`) register within the time set by `Control3` register Bit[12:11], RAA489118 terminates charging. After the timeout occurs, writing the `MaxSystemVoltage`(`0x15`) or `ChargeCurrentLimit`(`0x14`) register re-enables charging.<br>`0` = Enable the SMBus timeout function (default)<br>`1` = Disable the SMBus timeout function<br>For battery-charging only mode (`CONFIG` tied to VDD), this bit is irrelevant and the SMBus Timeout feature is always disabled. |
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| `[6:5]` | High-Side FET Short Detection Threshold | Bit[6:5] configures the high-side FET short detection phase node voltage threshold while the low-side FET turns on.<br>`00` = 800mV (default)<br>`01` = 500mV<br>`10` = 600mV<br>`11` = 400mV |
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<!-- page 33 -->
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**Table 3. Control0 Register 0x39H (Cont.)**
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| Bit | Bit Name | Description |
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| --- | --- | --- |
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| `[4:3]` | DCProchot# Threshold in Battery Only Low Power Mode | `Control7`[1] and `Control0`[4:3] configure the battery discharging current `DCProchot#` threshold in battery only Low Power mode as indicated by `Information1` register `0x3A` Bit[15]. If PSYS is enabled, the battery discharge current `DCProchot#` threshold is instead set by the `DCProchot#` register `0x48` setting.<br><table><thead><tr><th>Control7[1]</th><th>Control0[4:3]</th><th>R<sub>s2</sub> = 20mΩ (A)</th><th>R<sub>s2</sub> = 10mΩ (A)</th><th>R<sub>s2</sub> = 5mΩ (A)</th></tr></thead><tbody><tr><td>0 (default)</td><td>00 (default)</td><td>6</td><td>12</td><td>24</td></tr><tr><td>0</td><td>01</td><td>5</td><td>10</td><td>20</td></tr><tr><td>0</td><td>10</td><td>4</td><td>8</td><td>16</td></tr><tr><td>0</td><td>11</td><td>3</td><td>6</td><td>12</td></tr><tr><td>1</td><td>00</td><td>2.5</td><td>5</td><td>10</td></tr><tr><td>1</td><td>01</td><td>2</td><td>4</td><td>8</td></tr><tr><td>1</td><td>10</td><td>1.5</td><td>3</td><td>6</td></tr><tr><td>1</td><td>11</td><td>1</td><td>2</td><td>4</td></tr></tbody></table> |
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| `[2]` | Input Voltage Regulation Loop | Bit[2] enables or disables the input voltage regulation loop.<br>`0` = Enable the input voltage regulation loop (default)<br>`1` = Disable the input voltage regulation loop |
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| `[1]` | Force Buck Mode | Bit[1] disables or enables Force Buck mode. If the Force Buck mode bit is enabled, the Buck-Boost window narrows.<br>`0` = Disable Force Buck mode (default)<br>`1` = Enable Force Buck mode |
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**Table 4. Control1 Register 0x3CH**
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| Bit | Bit Name | Description |
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| --- | --- | --- |
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| `[15:14]` | General Purpose Comparator Assertion Debounce Time | Bit[15:14] configures the general purpose comparator assertion debounce time.<br>`00` = 2µs (default)<br>`01` = 12µs<br>`10` = 2ms<br>`11` = 5s |
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| `[13]` | Exit Learn Mode Option | Bit[13] provides the option to Exit Learn mode when the battery voltage is lower than the `MinSystemVoltage` register setting.<br>`0` = Stay in Learn mode even if V<sub>BAT</sub> < `MinSystemVoltage` register setting (default)<br>`1` = Exit Learn mode if V<sub>BAT</sub> < `MinSystemVoltage` register setting |
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| `[12]` | Learn Mode | Bit[12] enables or disables Battery Learn mode.<br>`0` = Disable Battery Learn mode (default)<br>`1` = Enable Battery Learn mode<br>To enter Learn mode, the `BATGONE` pin must be low, that is, the battery must be present. Renesas recommends to disable the slew rate control (`Control6` Bit[6] = `0`) when using Learn mode. |
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| `[11]` | OTG Function | Bit[11] enables or disables the OTG function.<br>`0` = Disable the OTG function (default)<br>`1` = Enable the OTG function |
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<!-- page 34 -->
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**Table 4. Control1 Register 0x3CH (Cont.)**
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| Bit | Bit Name | Description |
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| --- | --- | --- |
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| `[10]` | Audio Filter | Bit[10] enables or disables the audio filter function.<br>`0` = Disable the audio filter function (default)<br>`1` = Enable the audio filter function |
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| `[9:8]` | Switching Frequency | Bit[9:8] configures the switching frequency.<br>`00` = 1MHz<br>`01` = 839kHz<br>`10` = 732kHz (default)<br>`11` = 635kHz |
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| `[7]` | Not Used | Not used |
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| `[6]` | Turbo | Bit[6] enables or disables Turbo mode. When the turbo function is enabled, the `BGATE` FET turns on in Turbo mode. See Table 15 for the `BGATE` ON/OFF truth table.<br>`0` = Enable Turbo mode (default)<br>`1` = Disable Turbo mode |
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| `[5]` | AMON/BMON Function | Bit[5] enables or disables the current monitor function AMON and BMON.<br>`0` = Enable AMON/BMON (default)<br>`1` = Disable AMON/BMON<br>Bit[5] is only valid in Battery Only mode. When the adapter is present, AMON/BMON is automatically enabled and Bit[5] becomes invalid. |
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| `[4]` | AMON or BMON | Bit[4] selects AMON or BMON as the `AMON/BMON` pin output.<br>`0` = AMON (default)<br>`1` = BMON |
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| `[3]` | PSYS | Bit[3] enables or disables the system power monitor PSYS function.<br>`0` = Disables the PSYS function (default)<br>`1` = Enables the PSYS function |
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| `[2]` | VSYS | Bit[2] enables or disables the buck-boost charger switching VSYS output. When disabled, the RAA489118 stops switching and forces the `BGATE` FET on.<br>`0` = Enables VSYS output (default)<br>`1` = Disables VSYS output |
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| `[1:0]` | Low_VSYS_Prochot# Reference | Bit[1:0] configures the `Low_VSYS_Prochot#` assertion.<br>`00` = 6.0V (default)<br>`01` = 6.3V<br>`10` = 6.6V<br>`11` = 6.9V |
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<!-- page 35 -->
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**Table 5. Control2 Register 0x3DH**
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| Bit | Bit Name | Description |
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| --- | --- | --- |
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| `[15:14]` | Trickle Charging Current | Bit[15:14] configures the charging current in Trickle Charging mode.<br>`00` = 512mA (default)<br>`01` = 256mA<br>`10` = 128mA<br>`11` = 1024mA |
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| `[13]` | OTG Function Enable Debounce Time | Control2 Bit[13] and Control 3 Bit[0] configures the OTG function debounce time from when the RAA489118 receives the OTG enable command.<br><table><thead><tr><th>Control2[13]</th><th>Control3[0]</th><th>OTG Start-Up Delay</th></tr></thead><tbody><tr><td>0 (default)</td><td>0 (default)</td><td>1.3s</td></tr><tr><td>0</td><td>1</td><td>1.3s</td></tr><tr><td>1</td><td>0</td><td>150ms</td></tr><tr><td>1</td><td>1</td><td>7.5ms</td></tr></tbody></table> |
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| `[12]` | Two-Level Adapter Current Limit Function | Bit[12] enables or disables the two-level adapter current limit function.<br>`0` = Disables the two-level current limit function (default)<br>`1` = Enables the two-level current limit function |
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| `[11]` | Adapter Insertion to Switching Debounce | Bit[11] configures the debounce time from adapter insertion to when `ACOK` is asserted high.<br>`0` = 1.3s (default)<br>`1` = 150ms<br>After VDD POR, for the first time the adapter is plugged in, the ASGATE turn-on delay is always 150ms, regardless of the Bit[11] setting. This bit sets the ASGATE turn-on delay only after ASGATE turns off at least one time when VDD is above its POR value and the Bit[11] default is 0 for 1.3s. |
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| `[10:9]` | Prochot# Debounce | Bit[10:9] configures the `PROCHOT#` debounce time before its assertion for ACProchot# and DCProchot#. The Low_VSYS_Prochot# has a fixed 8µs debounce time.<br>`00`: 7µs (default)<br>`01`: 100µs<br>`10`: 500µs<br>`11`: 1ms |
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| `[8:6]` | Prochot# Duration | Bit[8:6] configures the minimum duration of the `PROCHOT#` signal when asserted.<br>`000` = 10ms (default)<br>`001` = 20ms<br>`010` = 15ms<br>`011` = 5ms<br>`100` = 1ms<br>`101` = 500µs<br>`110` = 100µs<br>`111` = 0s |
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| `[5]` | ASGATE in OTG Mode | Bit[5] turns the ASGATE FET on or off in OTG mode.<br>`0` = Turn on ASGATE in OTG mode (default)<br>`1` = Turn off ASGATE in OTG mode |
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<!-- page 36 -->
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**Table 5. Control2 Register 0x3DH (Cont.)**
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| Bit | Bit Name | Description |
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| --- | --- | --- |
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| `[4]` | CMIN Reference | Bit[4] configures the general purpose comparator reference voltage when an adapter is attached. (In Battery-Only low-power mode, the reference voltage is 1.2V regardless of this bit.)<br>`0` = 1.2V (default)<br>`1` = 2V |
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| `[3]` | General Purpose Comparator | Bit[3] enables or disables the general purpose comparator.<br>`0` = Enable the general purpose comparator (default)<br>`1` = Disable the general purpose comparator |
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| `[2]` | CMOUT Polarity | Bit[2] configures the general purpose comparator output polarity when asserted. The comparator reference voltage is connected at the inverting input node.<br>`0` = `CMOUT` is High when `CMIN` is higher than reference (default)<br>`1` = `CMOUT` is Low when `CMIN` is higher than reference |
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| `[1:0]` | Pass-Through Mode | Bit[1:0] configures the Pass-Through Mode (PTM).<br>`00` = Disable normal PTM and forced PTM (default)<br>`01` = Enable normal PTM<br>`10` = Not Used<br>`11` = Enable Forced PTM |
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**Table 6. Control3 Register 0x4CH**
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| Bit | Bit Name | Description<sup>7</sup> |
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| --- | --- | --- |
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| `[15]` | Reread PROG Pin Resistor | Bit[15] specifies whether to reread the `PROG` pin resistor.<br>`0` = Reread `PROG` pin resistor (default)<br>`1` = Do not reread `PROG` pin resistor |
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| `[14]` | Reload ACLIM When Adapter Is Plugged In | Bit[14] specifies whether to reload the `AdapterCurrentLimit1` register set by the `PROG` pin resistor.<br>`0` = Reload the `AdapterCurrentLimit1` register (default)<br>`1` = Do not reload the `AdapterCurrentLimit1` register |
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| `[13]` | Autonomous Charging Termination Time | Bit[13] configures the autonomous charging termination time.<br>`0` = 20ms (default)<br>`1` = 200ms |
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| `[12:11]` | Charger Timeout | Bit[12:11] configures the SMBus charger timeout time.<br>`00` = 175s (default)<br>`01` = 87.5s<br>`10` = 43.75s<br>`11` = 5s |
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| `[10]` | BGATE Force OFF | Bit[10] configures the BGATE operation between normal and force off.<br>`0` = Normal BGATE operation (default)<br>`1` = Force BGATE MOSFET off |
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| `[9]` | PSYS Gain | Bit[9] configures the system power monitor `PSYS` output gain.<br>`0` = 0.236µA/W (default)<br>`1` = 0.118µA/W |
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<!-- page 37 -->
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**Table 6. Control3 Register 0x4CH (Cont.)**
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| Bit | Bit Name | Description<sup>7</sup> |
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| --- | --- | --- |
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| `[8]` | Exit IDM Timer | Control7[7] and Control3[8] configure the Ideal Diode mode exit timer when the battery discharge current is less than 380mA.<br><table><thead><tr><th>Control3 [8]</th><th>Control7 [7]</th><th>IDM Timer</th></tr></thead><tbody><tr><td>0 (default)</td><td>0 (default)</td><td>40ms</td></tr><tr><td>0</td><td>1</td><td>5ms</td></tr><tr><td>1</td><td>0</td><td>80ms</td></tr><tr><td>1</td><td>1</td><td>1ms</td></tr></tbody></table> |
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| `[7]` | Charging Mode | Bit[7] selects the charging mode.<br>`0` = Enable Autonomous Charging mode<br>`1` = Battery charging current control through SMBus<br>Default is determined by `PROG` and `CONFIG`. |
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| `[6]` | AC and CC Feedback Gain | Bit[6] configures AC and CC feedback gain for high current.<br>`0` = x1 (default)<br>`1` = x0.5 |
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| `[5]` | Adapter-Side Current Limit Loop | Bit[5] enables or disables the adapter-side input current limit loops for forward and reverse/OTG modes.<br>`0` = Enable adapter-side current limit loops (default)<br>`1` = Disable adapter-side current limit loops |
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| `[4]` | Adapter-Side Current Limit Loop when BATGONE = 1 | Bit[4] enables or disables the adapter-side current limit loop, in forward mode, when `BATGONE` = 1.<br>`0` = Enable adapter-side current limit loop when `BATGONE` = 1 (default)<br>`1` = Disable adapter-side current limit loop when `BATGONE` = 1 |
|
||
| `[3]` | AMON/BMON Direction | Bit[3] configures the `AMON`/`BMON` direction.<br>`0` = Adapter current monitor/battery charging current monitor (default)<br>`1` = OTG output current monitor/battery discharging current monitor |
|
||
| `[2]` | Digital Reset | Bit[2] resets all SMBus register values to the POR default value.<br>`0` = Idle (default)<br>`1` = Reset |
|
||
| `[1]` | Buck-Boost Stretch CCM Period | Control3 Bit[1] and Control4 Bit[8] configure the Buck-Boost stretch CCM period (T2 TIME).<br><table><thead><tr><th>Control3[1]</th><th>Control4[8]</th><th>T2 Time</th></tr></thead><tbody><tr><td>0</td><td>0</td><td>0.6x (default)</td></tr><tr><td>0</td><td>1</td><td>1x</td></tr><tr><td>1</td><td>0</td><td>3x</td></tr><tr><td>1</td><td>1</td><td>2x</td></tr></tbody></table> |
|
||
| `[0]` | OTG Start-Up Delay | Refer to the description of Control2[13] in Table 5. |
|
||
|
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<!-- page 38 -->
|
||
|
||
**Table 7. Control4 Register 0x4EH**
|
||
|
||
| Bit | Bit Name | Description |
|
||
| --- | --- | --- |
|
||
| `[15:14]` | Dither Enable | Bit[15:14] disables or selects the switching frequency dithering function.<br>`00` = Disable dither (default)<br>`01` = Dither 100 - 102%<br>`10` = Dither 100 - 104%<br>`11` = Dither 100 - 106% |
|
||
| `[13]` | ADP Discharge | Bit[13] enables or disables the ADP discharge function. Typical 10mA.<br>`0` = Disable ADP discharge function (default)<br>`1` = Enable ADP discharge function |
|
||
| `[12]` | VSYS Sink | Bit[12] enables or disables the `VSYS` discharge function. Typical 10mA.<br>`0` = Disable `VSYS` discharge function (default)<br>`1` = Enable `VSYS` discharge function |
|
||
| `[11]` | BGATE Tri-state | Bit[11] enables or disables the BGATE tri-state function.<br>`0` = Disable BGATE tri-state (default)<br>`1` = Enable BGATE tri-state |
|
||
| `[10]` | Buck-Boost Min T3 Time | Bit[10] selects the minimum T3 time when in the buck-boost mode.<br>`0` = Long (default)<br>`1` = Short |
|
||
| `[9]` | Buck-Boost T2 time in DCM | Bit[9] selects the buck-boost T2 time in the discontinuous-conduction mode (DCM).<br>`0` = Reduced T2 time (increases switching frequency in DCM) (default)<br>`1` = Normal T2 time |
|
||
| `[8]` | Buck-Boost Stretch CCM Period | Refer to the description of Control3 Bit[1] in Table 6. |
|
||
| `[7]` | OTGCURRENT PROCHOT# | Bit[7] enables or disables `PROCHOT#` trigger with `OTGCURRENT`.<br>`0` = Disable `PROCHOT#` trigger with `OTGCURRENT` (default)<br>`1` = Enable `PROCHOT#` trigger with `OTGCURRENT` |
|
||
| `[6]` | BATGONE PROCHOT# | Bit[6] enables or disables `PROCHOT#` trigger with `BATGONE`.<br>`0` = Disable `PROCHOT#` trigger with `BATGONE` (default)<br>`1` = Enable `PROCHOT#` trigger with `BATGONE` |
|
||
| `[5]` | ACOK PROCHOT# | Bit[5] enables or disables `PROCHOT#` trigger with `ACOK`.<br>`0` = Disable `PROCHOT#` trigger with `ACOK` (default)<br>`1` = Enable `PROCHOT#` trigger with `ACOK` |
|
||
| `[4]` | Comparator PROCHOT# | Bit[4] enables or disables `PROCHOT#` trigger with General Purpose Comparator rising.<br>`0` = Disable `PROCHOT#` trigger with General Purpose Comparator rising (default)<br>`1` = Enable `PROCHOT#` trigger with General Purpose Comparator rising |
|
||
| `[3:2]` | ACOK falling or BATGONE Rising Debounce | Bit[3:2] configures the debounce time from `ACOK` falling or `BATGONE` rising to `PROCHOT#` trip.<br>`00` = 2µs (default)<br>`01` = 25µs<br>`10` = 125µs<br>`11` = 250µs |
|
||
|
||
<!-- page 39 -->
|
||
|
||
**Table 7. Control4 Register 0x4EH (Cont.)**
|
||
|
||
| Bit | Bit Name | Description |
|
||
| --- | --- | --- |
|
||
| `[1]` | PROCHOT# Clear | Bit[1] clears `PROCHOT#`.<br>`0` = Idle (default)<br>`1` = Clear `PROCHOT#` |
|
||
| `[0]` | PROCHOT# Latch | Bit[0] manually resets `PROCHOT#`.<br>`0` = `PROCHOT#` signal auto-clear (default)<br>`1` = Latch `PROCHOT#` low when tripped |
|
||
|
||
**Table 8. Control5 Register 0x38H**
|
||
|
||
| Bit | Bit Name | Descriptions |
|
||
| --- | --- | --- |
|
||
| `[15:14]` | Internal Compensation Resistance | Bit[15:14] set the internal compensation resistance<br>`00` = 1.26 KΩ (default)<br>`01` = 773Ω<br>`10` = 3.6 KΩ<br>`11` = 1.88 KΩ |
|
||
| `[13]` | Force BGATE On | Bit[13] enables or disables the Force BGATE On function<br>`0` = Normal BGATE operation (default)<br>`1` = Force BGATE On |
|
||
| `[12]` | Unused | - |
|
||
| `[11]` | VBAT Regulation Loop in OTG Mode | Bit[11] enables or disables the VBAT (VIN) voltage regulation during OTG (reverse) mode<br>`0` = Disable (default)<br>`1` = Enable |
|
||
| `[10:8]` | Two-Level ACLIM T2 Time | Bit[10:8] sets the T2 time corresponding to `AdapterCurrentLimit2` when two-level adapter current limit function is enabled.<br>`000` = 10µs (default)<br>`001` = 100µs<br>`010` = 500µs<br>`011` = 1ms<br>`100` = 300µs<br>`101` = 750µs<br>`110` = 2ms<br>`111` = 10ms |
|
||
| `[7]` | VSYSOK 0.6V Comparator | Bit[7] enables or disables the 0.6V comparator.<br>`0` = Enable (default)<br>`1` = Disable |
|
||
| `[6]` | VSYSOK 10mA Current Source | Bit[6] enables or disables the 10mA current source.<br>`0` = Enable (default)<br>`1` = Disable |
|
||
| `[5]` | OTGPG/CMOUT Selection | Bit[5] selects the signal routed to the `OTGPG`/`CMOUT` pin.<br>`0` = `OTGPG` (default)<br>`1` = `CMOUT` |
|
||
| `[4]` | VSYSOV/OTGOV Control | Bit[4] enables or disables `VSYS` and OTG overvoltage protections.<br>`0` = Enable (default)<br>`1` = Disable |
|
||
|
||
<!-- page 40 -->
|
||
|
||
**Table 8. Control5 Register 0x38H**
|
||
|
||
| Bit | Bit Name | Descriptions |
|
||
| --- | --- | --- |
|
||
| `[3]` | Unused | - |
|
||
| `[2:0]` | Two-Level ACLIM T1 Time | Bit[2:0] sets the T1 time corresponding to `AdapterCurrentLimit1` when two-level adapter current limit function is enabled.<br>`000` = 10ms (default)<br>`001` = 20ms<br>`010` = 15ms<br>`011` = 5ms<br>`100` = 1ms<br>`101` = 0.5ms<br>`110` = 0.1ms<br>`111` = 0ms |
|
||
|
||
**Table 9. Control6 Register 0x37H**
|
||
|
||
| Bit | Bit Name | Description |
|
||
| --- | --- | --- |
|
||
| `[15:8]` | Not Used | Not used |
|
||
| `[7]` | Turn off BGATE at VSYSOV | Bit[7] configures the BGATE behavior during `VSYS` overvoltage.<br>`0` = No action (default)<br>`1` = Turn off BGATE |
|
||
| `[6]` | Slew Rate Control for Charge Current, Maximum System Voltage, and OTG Voltage | Bit[6] enables or disables the slew rate control for charger current, maximum system voltage, and OTG voltage.<br>`0` = Disable the slew rate control<br>`1` = Enable the slew rate control (default)<br>Slew is limited to 1 DAC LSB per 16 clock cycles (1µs each). Nominal slew rates: 1mV/µs for system voltage, 0.5mA/µs for charging current with R<sub>s2</sub> = 5mΩ, and 1.125mV/µs for OTG voltage. |
|
||
| `[5]` | OTG Undervoltage Protection | Bit[5] enables or disables the OTG undervoltage protection<br>`0` = Enable OTG undervoltage protection (default)<br>`1` = Disable OTG undervoltage protection |
|
||
| `[4]` | Clear CMOUT Latch Data | Bit[4] clears the current `CMOUT` data when written to 1. The `CMOUT` latch data can be read from Bit[4] when Control6[3] = 0 (`CMOUT` Latch is enabled).<br>`0` = Do not clear `CMOUT` latch data (default)<br>`1` = Clear `CMOUT` latch data |
|
||
| `[3]` | CMOUT Latch | Bit[3] enables or disables the `CMOUT` latch function.<br>`0` = Enable the `CMOUT` latch function (default)<br>`1` = Disable the `CMOUT` latch function |
|
||
| `[2:0]` | VSYS Undervoltage Threshold | Bit[2:0] set `VSYS` under voltage threshold.<br>`000` = Disable (default when `CONFIG` = VDD or when inserting the battery for the first time)<br>`001` = 3.0V<br>`010` = 3.9V<br>`011` = 4.8V (default when `CONFIG` pulled low, except after inserting battery for the first time)<br>`100` = 5.7V<br>`101` = 6.6V<br>`110` = 7.5V<br>`111` = 8.4V |
|
||
|
||
<!-- page 41 -->
|
||
|
||
**Table 10. Control7 Register 0x36H**
|
||
|
||
| Bit | Bit Name | Description |
|
||
| --- | --- | --- |
|
||
| `[15:8]` | Not Used | Not Used |
|
||
| `[7]` | Exit IDM Timer | `Control7[7]` and `Control3[8]` configure the Ideal Diode mode exit timer when the battery discharge current is less than 380mA.<br><table><thead><tr><th>Control3[8]</th><th>Control7[7]</th><th>IDM Timer</th></tr></thead><tbody><tr><td>0 (default)</td><td>0 (default)</td><td>40ms (default)</td></tr><tr><td>0</td><td>1</td><td>5ms</td></tr><tr><td>1</td><td>0</td><td>80ms</td></tr><tr><td>1</td><td>1</td><td>1ms</td></tr></tbody></table> |
|
||
| `[6:2]` | Not Used | Not Used |
|
||
| `[1]` | Battery Only DCProchot# Threshold | Refer to the description of `Control0[4:3]` in Table 3. |
|
||
| `[0]` | VSYS ABS OV | VSYS absolute overvoltage protection<br>`0` = Enabled (default)<br>`1` = Disabled |
|
||
|
||
## 6.4 Information Registers
|
||
|
||
The Information registers contain SMBus readable information about manufacturing and Operating modes. The following tables identify the bit locations of the available information.
|
||
|
||
**Table 11. Information1 Register 0x3AH**
|
||
|
||
| Bit | Description |
|
||
| --- | --- |
|
||
| `[3:0]` | Not used |
|
||
| `[4]` | `Bit[4]` indicates whether the Trickle Charging mode is active.<br>`0` = Trickle Charging mode is not active<br>`1` = Trickle Charging mode is active |
|
||
| `[9:5]` | Not used |
|
||
| `[10]` | `Bit[10]` indicates whether the `Low_VSYS_Prochot#` is tripped.<br>`0` = `Low_VSYS_Prochot#` is not tripped<br>`1` = `Low_VSYS_Prochot#` is tripped |
|
||
| `[11]` | `Bit[11]` indicates whether `DCProchot#` is tripped.<br>`0` = `DCProchot#` is not tripped<br>`1` = `DCProchot#` is tripped |
|
||
| `[12]` | `Bit[12]` indicates whether `ACProchot#`/`OTGCURRENTProchot#` is tripped.<br>`0` = `ACProchot#`/`OTGCURRENTProchot#` is not tripped<br>`1` = `ACProchot#`/`OTGCURRENTProchot#` is tripped |
|
||
|
||
<!-- page 42 -->
|
||
|
||
**Table 11. Information1 Register 0x3AH (Cont.)**
|
||
|
||
| Bit | Description |
|
||
| --- | --- |
|
||
| `[14:13]` | `Bit[14:13]` indicates the active control loop.<br>`00` = MaxSystemVoltage control loop is active<br>`01` = Charging current loop is active<br>`10` = Adapter current limit loop is active<br>`11` = Input voltage loop is active |
|
||
| `[15]` | `Bit[15]` indicates whether the internal reference circuit is active. `Bit[15]` = 0 indicates that the RAA489118 is in Low Power mode.<br>`0` = Reference is not active<br>`1` = Reference is active |
|
||
|
||
**Table 12. Information2 Register 0x4DH**
|
||
|
||
| Bit | Description |
|
||
| --- | --- |
|
||
| `[4:0]` | Program Resister read out<br>MaximumSystemVoltage<br>MinimumSystemVoltage<br>Adapter current limit |
|
||
| `[7:5]` | `Bit[7:5]` indicates the RAA489118 operation mode.<br>`001` = Boost Mode<br>`010` = Buck Mode<br>`011` = Buck-Boost Mode<br>`101` = OTG Boost Mode<br>`110` = OTG Buck Mode<br>`111` = OTG Buck-Boost Mode |
|
||
| `[11:8]` | `Bit[11:8]` indicates the RAA489118 state machine status.<br>`0000` = OFF<br>`0001` = BATTERY<br>`0010` = ADAPTER<br>`0011` = ACOK<br>`0100` = VSYS<br>`0101` = CHARGE<br>`0110` = ENOTG<br>`0111` = OTG<br>`1000` = ENLDO5<br>`1001` = Not Applicable<br>`1010` = TRIM/ENCHREF<br>`1011` = ACHRG<br>`1100` = CAL<br>`1101` = AGON/AGONTG<br>`1110` = WAIT/PSYS<br>`1111` = ADPPSYS |
|
||
| `[12]` | `Bit[12]` indicates the `BATGONE` pin status.<br>`0` = Battery is present (`BATGONE` low)<br>`1` = No battery (`BATGONE` high) |
|
||
| `[13]` | `Bit[13]` indicates the general purpose comparator output after debounce time.<br>`0` = Comparator output is low<br>`1` = Comparator output is high |
|
||
|
||
<!-- page 43 -->
|
||
|
||
**Table 12. Information2 Register 0x4DH (Cont.)**
|
||
|
||
| Bit | Description |
|
||
| --- | --- |
|
||
| `[14]` | `Bit[14]` indicates the `ACOK` pin status.<br>`0` = No adapter<br>`1` = Adapter is present |
|
||
| `[15]` | `Bit[15]` indicates the `CONFIG/PSYS` state.<br>`0` = `CONFIG/PSYS` pulled low (NVDC Charging with BFET)<br>`1` = `CONFIG/PSYS` tied to `VDD` (Battery charging only with no BFET) |
|
||
|
||
**Table 13. Information3 Register 0x90H**
|
||
|
||
| Bit | Description |
|
||
| --- | --- |
|
||
| `[15:2]` | Not used |
|
||
| `[1]` | `Bit[1]` indicates the Pass-Through Mode (PTM) status.<br>`0` = PTM is inactive<br>`1` = PTM is active |
|
||
| `[0]` | Not used |
|