add REN_RAA489400

REN_RAA489400/01-overview.md

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+<!-- page 5 -->
+
+# RAA489400 Datasheet
+
+## 1. Overview
+
+### 1.1 Block Diagram
+
+![Figure 1. Block Diagram](01-overview/figure-01.png)
+
+**Figure 1. Block Diagram**
+
+---
+
+<!-- page 6 -->
+
+### 1.2 Typical Application
+
+![Figure 2. Typical USB-C Application Based on TCPC and TCPM for DRP (Dual Role Power) System, Supports VBUS SNK: Up to 48V and SRC: Up to 5V](01-overview/figure-02.png)
+
+**Figure 2. Typical USB-C Application Based on TCPC and TCPM for DRP (Dual Role Power) System, Supports VBUS SNK: Up to 48V and SRC: Up to 5V**
+
+![Figure 3. Typical USB-C Application Based on TCPC and TCPM for Source Only System, Supports VBUS SRC: Up to 5V](01-overview/figure-03.png)
+
+**Figure 3. Typical USB-C Application Based on TCPC and TCPM for Source Only System, Supports VBUS SRC: Up to 5V**
+
+---
+
+<!-- page 7 -->
+
+![Figure 4. Typical USB-C Application Based on TCPC and TCPM for Sink Only System, Supports VBUS SNK: Up to 48V](01-overview/figure-04.png)
+
+**Figure 4. Typical USB-C Application Based on TCPC and TCPM for Sink Only System, Supports VBUS SNK: Up to 48V**
+
+![Figure 5. Typical USB-C Application Based on TCPC and TCPM for DRP System with GPIO Control](01-overview/figure-05.png)
+
+**Figure 5. Typical USB-C Application Based on TCPC and TCPM for DRP System with GPIO Control**
+
+---
+
+<!-- page 8 -->
+
+![Figure 6. Typical USB-C Application based on TCPC and TCPM for Source Only System with GPIO Control](01-overview/figure-06.png)
+
+**Figure 6. Typical USB-C Application based on TCPC and TCPM for Source Only System with GPIO Control**
+
+![Figure 7. Typical USB-C Application Based on TCPC and TCPM for Sink Only System with GPIO Control](01-overview/figure-07.png)
+
+**Figure 7. Typical USB-C Application Based on TCPC and TCPM for Sink Only System with GPIO Control**
+
+---
+
+<!-- page 9 -->
+
+![Figure 8. Example of USB-C Application Based on TCPC and TCPM for DRP (Dual Role Power) System with VSNK_GATE and GPIO Control, Supports VBUS SNK: Up to 48V and SRC: Up to 48V](01-overview/figure-08.png)
+
+**Figure 8. Example of USB-C Application Based on TCPC and TCPM for DRP (Dual Role Power) System with VSNK_GATE and GPIO Control, Supports VBUS SNK: Up to 48V and SRC: Up to 48V**
+
+---
+
+<!-- page 10 -->
+
+![Figure 9. Example of USB-C Application Based on TCPC and TCPM for Bi-directional DRP (Dual Role Power) System with GPIO Control, Supports VBUS SNK: Up to 48V and SRC: Up to 48V](01-overview/figure-09.png)
+
+**Figure 9. Example of USB-C Application Based on TCPC and TCPM for Bi-directional DRP (Dual Role Power) System with GPIO Control, Supports VBUS SNK: Up to 48V and SRC: Up to 48V**

REN_RAA489400/02-pin-information.md

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+# RAA489400 Datasheet
+
+<!-- page 11 -->
+
+## 2. Pin Information
+
+### 2.1 Pin Assignments
+
+![Figure 10. Pin Assignments – Top View](02-pin-information/figure-10.png)
+
+Pin numbers and names read from the drawing:
+
+| Side | Pin Number | Pin Name |
+|---|---|---|
+| Left | 1 | `NC` |
+| Left | 2 | `CC1` |
+| Left | 3 | `RD1` |
+| Left | 4 | `VDD25` |
+| Left | 5 | `GPIO4` |
+| Left | 6 | `GPIO3` |
+| Left | 7 | `GPIO2` |
+| Left | 8 | `GPIO1` |
+| Left | 9 | `OCP#` |
+| Left | 10 | `PROG` |
+| Left | 11 | `NC` |
+| Bottom | 12 | `VSYS33` |
+| Bottom | 13 | `VDD33` |
+| Bottom | 14 | `VBUS` |
+| Bottom | 15 | `CSIP` |
+| Bottom | 16 | `CSIN` |
+| Right | 17 | `NC` |
+| Right | 18 | `VSNK_GATE` |
+| Right | 19 | `VSNK_SRC` |
+| Right | 20 | `SNK_DISCHG` |
+| Right | 21 | `VSRC_GATE` |
+| Right | 22 | `VSRC_SRC` |
+| Right | 23 | `VSRC_BOOT` |
+| Right | 24 | `GND` |
+| Right | 25 | `RD2` |
+| Right | 26 | `CC2` |
+| Right | 27 | `NC` |
+| Top | 28 | `SCL` |
+| Top | 29 | `SDA` |
+| Top | 30 | `VCONN_POWER` |
+| Top | 31 | `ALERT#` |
+| Top | 32 | `PROCHOT#` |
+| Exposed pad | `CC1_EP` | `CC1` exposed pad |
+| Exposed pad | `CC2_EP` | `CC2` exposed pad |
+
+### 2.2 Pin Descriptions
+
+| Pin Number | Pin Name | Description |
+|---|---|---|
+| 1 | `NC` | No connection |
+| 2 | `CC1` | Configuration Channel 1, Analog pin from CC-PHY. |
+| 3 | `RD1` | Dead battery Rd, Analog pin from CC-PHY. Tie to `CC1` when dead battery Rd is supported. |
+| 4 | `VDD25` | 2.5V LDO output provides the bias power for internal digital logic and the TCPC transmitter. Connect a ceramic capacitor to GND. The effective capacitance of `VDD25` capacitor should be at least 1µF at 2.5V. This pin cannot source current to external circuits. |
+<!-- page 12 -->
+| 5 | `GPIO4` | General purpose input and output with a 3.3V push-pull output, 1.8V or 3.3V open-drain output, 1.8V or 3.3V input, or disable. It can be used as a VBUS source or a sink switch control and overcurrent input.<br>• VBUS source power switch enable<br>• VBUS sink power switch enable<br>• Overcurrent Input (from external VBUS source power switch)<br>• General Purpose Input<br>• General Purpose Output (push-pull)<br>• General Purpose Output (open-drain)<br>`GPIO1_CTRL` Register, `GPIO2_CTRL` Register, `GPIO3_CTRL` Register, `GPIO4_CTRL` Register, `VBUS_PATH_CTRL` Register, `VBUS_GPIO_CTRL` Register, and `GPIO_OC_EN` Register control those configurations. |
+| 6 | `GPIO3` | General purpose input and output with a 3.3V push-pull output, 1.8V or 3.3V open-drain output, 1.8V or 3.3V input, or disable. It can be used as a VBUS source or a sink switch control and overcurrent input.<br>• VBUS source power switch enable<br>• VBUS sink power switch enable<br>• Overcurrent Input (from external VBUS source power switch)<br>• General Purpose Input<br>• General Purpose Output (push-pull)<br>• General Purpose Output (open-drain)<br>`GPIO1_CTRL` Register, `GPIO2_CTRL` Register, `GPIO3_CTRL` Register, `GPIO4_CTRL` Register, `VBUS_PATH_CTRL` Register, `VBUS_GPIO_CTRL` Register, and `GPIO_OC_EN` Register control those configurations. |
+| 7 | `GPIO2` | General purpose input and output with a 3.3V push-pull output, 1.8V or 3.3V open-drain output, 1.8V or 3.3V input, or disable. It can be used as a VBUS source or a sink switch control and overcurrent input.<br>• VBUS source power switch enable<br>• VBUS sink power switch enable<br>• Overcurrent Input (from external VBUS source power switch)<br>• General Purpose Input<br>• General Purpose Output (push-pull)<br>• General Purpose Output (open-drain)<br>`GPIO1_CTRL` Register, `GPIO2_CTRL` Register, `GPIO3_CTRL` Register, `GPIO4_CTRL` Register, `VBUS_PATH_CTRL` Register, `VBUS_GPIO_CTRL` Register, and `GPIO_OC_EN` Register control those configurations. |
+| 8 | `GPIO1` | General purpose input and output with a 3.3V push-pull output, 1.8V or 3.3V open-drain output, 1.8V or 3.3V input, or disable. It can be used as a VBUS source or a sink switch control and overcurrent input.<br>• VBUS source power switch enable<br>• VBUS sink power switch enable<br>• Overcurrent Input (from external VBUS source power switch)<br>• General Purpose Input<br>• General Purpose Output (push-pull)<br>• General Purpose Output (open-drain)<br>`GPIO1_CTRL` Register, `GPIO2_CTRL` Register, `GPIO3_CTRL` Register, `GPIO4_CTRL` Register, `VBUS_PATH_CTRL` Register, `VBUS_GPIO_CTRL` Register, and `GPIO_OC_EN` Register control those configurations. |
+| 9 | `OCP#` | Open-drain output with 1.8V or 3.3V pull-up.<br>Active low when a fault condition configured in `OCP_OUTPUT_CTRL` Register (A8h) is detected.<br>When all fault conditions are removed, `OCP#` pin is deasserted to high. |
+| 10 | `PROG` | A resistor from the `PROG` pin to GND to set the SMBus/I²C slave target address. |
+| 11 | `NC` | No connection |
+| 12 | `VSYS33` | Main power input (minimum 3.0V, typical 3.3V). Connect a ceramic capacitor to GND. Recommended capacitance: 4.7µF. |
+| 13 | `VDD33` | 3.3V LDO output provides the bias power for the internal analog and digital circuit. It also supplies power for the external TCPM.<br>Connect a ceramic capacitor to GND. The effective capacitance of `VDD33` capacitor should be at least 1µF at 3.3V.<br>Do not apply additional load on the `VDD33` pin other than TCPM and a pull-up resistor for `SDA`/`SCL`/`ALERT#` between RAA489400 and TCPM.<br>*Note:* If two or more RAA489400 `VDD33` supplies 3.3V to TCPM, a diode is required for each `VDD33` pin. |
+| 14 | `VBUS` | VBUS voltage sense and discharge input.<br>Input for internal LDO power on dead battery mode (`VSYS33` = 0V). |
+| 15 | `CSIP` | Connect to the VBUS source current-sense resistor positive input through a resistor. Place a ceramic capacitor between `CSIP` and `CSIN` to provide differential-mode filtering.<br>The current sense resistor value must be 10mΩ. |
+| 16 | `CSIN` | Input for sensing VBUS voltage. Connect to the VBUS source current-sense resistor negative input. Use a Kelvin line between the voltage sense point and `CSIN`. |
+| 17 | `NC` | No connection |
+| 18 | `VSNK_GATE` | Gate drive output of N-channel MOSFET USB-C/PD VBUS sink path FET. |
+| 19 | `VSNK_SRC` | N-channel MOSFET source input reference for USB-C/PD VBUS sink path FET(s). |
+| 20 | `SNK_DISCHG` | Internal system sink path discharge between the VBUS sink path gate and system load (such as battery charger adapter side). |
+| 21 | `VSRC_GATE` | Gate drive output of N-channel MOSFET USB-C/PD Source FET, pumped 5V above `VSRC_SRC`. |
+| 22 | `VSRC_SRC` | N-channel MOSFET source input reference for USB-C/PD VBUS Source path FET(s). |
+| 23 | `VSRC_BOOT` | Connect external capacitor for charge pump of `VSRC_GATE`.<br>Recommended capacitance: 0.047µF. |
+| 24 | `GND` | Ground |
+| 25 | `RD2` | Dead battery Rd, Analog pin from CC-PHY. Tie to `CC2` when dead battery Rd is supported. |
+| 26 | `CC2` | Configuration Channel 2, Analog pin from CC-PHY. |
+<!-- page 13 -->
+| 27 | `N.C.` | No connection |
+| 28 | `SCL` | SMBus/I²C clock I/O. Connect to the clock line from TCPM for TCPC control. |
+| 29 | `SDA` | SMBus/I²C data I/O. Connect to the data line from TCPM for TCPC control. |
+| 30 | `VCONN_POWER` | 5V Input to the VCONN MUX providing power to the `CC1`/`CC2` and the `VSRC_GATE` driver.<br>Connect a ceramic capacitor to GND.<br>The `VCONN_POWER` capacitor should be at least 4.7µF. |
+| 31 | `ALERT#` | Interrupt line for `SDA` and `SCL`. |
+| 32 | `PROCHOT#` | Open-drain output with 1.8V or 3.3V pull-up.<br>Active low when either VBUS source device disconnection or Sink Fast Role Swap is detected. The assertion condition configured in `PROCHOT_EN` Register (AAh) is detected.<br>When the condition is removed, the `PROCHOT#` pin is deasseted to high. |
+| `CC1-EP` | `CC1` | Exposed pad for `CC1`. |
+| `CC2-EP` | `CC2` | Exposed pad for `CC2`. |
+
+### 2.3 Unused Pin Termination
+
+| Pin Number | Pin Name | Connection Method |
+|---|---|---|
+| 1, 11, 17, 27 | `NC` | Open |
+| 3 | `RD1` | Open |
+| 5 | `GPIO4` | Open |
+| 6 | `GPIO3` | Open |
+| 7 | `GPIO2` | Open |
+| 8 | `GPIO1` | Open |
+| 9 | `OCP#` | Open |
+| 12 | `VSYS33` | Connect to GND if `VSYS33` is not used for start-up. |
+| 18 | `VSNK_GATE` | Open |
+| 19 | `VSNK_SRC` | Connect to GND through a 0Ω resistor. |
+| 21 | `VSRC_GATE` | Open |
+| 22 | `VSRC_SRC` | Connect to GND through a 0Ω resistor. |
+| 23 | `VSRC_BOOT` | Open |
+| 25 | `RD2` | Open |
+| 30 | `VCONN_POWER` | Connect to `VDD33` if VCONN function is not used. |
+| 32 | `PROCHOT#` | Open |
+
+Notes:
+
+1. In the original document, the description cell for pins 5–8 (`GPIO4`, `GPIO3`, `GPIO2`, `GPIO1`) is a single merged cell spanning all four rows; the text has been repeated for each pin row here.
+2. In the original document, the connection method cell for pins 5–8 (`GPIO4`, `GPIO3`, `GPIO2`, `GPIO1`) in the Unused Pin Termination table is a single merged cell containing "Open"; the value has been repeated for each pin row here.

REN_RAA489400/03-specifications.md

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+<!-- page 14 -->
+
+**RAA489400 Datasheet**
+
+# 3. Specifications
+
+## 3.1 Absolute Maximum Ratings
+
+*Caution:* Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions can adversely impact product reliability and result in failures not covered by warranty.
+
+| Parameter | Minimum | Maximum | Unit |
+| --- | --- | --- | --- |
+| `CC1`, `CC2`, `RD1`, `RD2`, `CSIN`, `CSIP`, `VBUS`, `SNK_DISCHG` | -0.3 | +60 | V |
+| `CSIP`-`CSIN` | -0.5 | +0.5 | V |
+| `VSNK_SRC` | -0.3 | +60 | V |
+| `VSNK_GATE` | -0.3 | +66.5 | V |
+| `VSNK_GATE` | `VSNK_SRC` - 0.3 | `VSNK_SRC` + 6.5 | V |
+| `VSRC_SRC` | -0.3 | +6.5 | V |
+| `VSRC_BOOT` | -0.3 | +13 | V |
+| `VSRC_BOOT` | `VSRC_SRC` - 0.3 | `VSRC_SRC` + 6.5 | V |
+| `VSRC_GATE` | -0.3 | +13.3 | V |
+| `VSRC_GATE` | `VSRC_SRC` - 0.3 | `VSRC_BOOT` + 0.3 | V |
+| `GPIO1`, `GPIO2`, `GPIO3`, `GPIO4` | -0.3 | +6.5 | V |
+| `OCP#`, `PROCHOT#`, `ALERT#` | -0.3 | +6.5 | V |
+| `PROG` | -0.3 | +6.5 | V |
+| `VSYS33`, `VDD33` | -0.3 | +6.5 | V |
+| `VDD25` | -0.3 | +3 | V |
+| `VCONN_POWER` | -0.3 | +6.5 | V |
+| `SDA`, `SCL` | -0.3 | +6.5 | V |
+| `GPIO1`, `GPIO2`, `GPIO3`, `GPIO4`, `SDA`, `SCL`, `OCP#`, `PROCHOT#`, `ALERT#` | - | 4 | mA |
+| Maximum Junction Temperature | -40 | +125 | °C |
+| Maximum Storage Temperature Range | -65 | +150 | °C |
+| Human Body Model (Tested per JS-001-2023) | -1.5 | 1.5 | kV |
+| Charged Device Model (Tested per JS-002-2022) | -0.75 | 0.75 | kV |
+| Latch-Up (Tested per JESD78E; Class 2, Level A) | - | 100 | mA |
+
+<!-- page 15 -->
+
+**RAA489400 Datasheet**
+
+## 3.2 Recommended Operating Conditions
+
+| Parameter | Minimum | Maximum | Unit |
+| --- | --- | --- | --- |
+| `VSYS33`, `VDD33` | -0.3 | +3.6 | V |
+| `VCONN_POWER` | -0.3 | +5.5 | V |
+| `CSIN`, `CSIP`, `VBUS`, `SNK_DISCHG` | -0.3 | +55 | V |
+| `VSNK_SRC` | -0.3 | +55 | V |
+| `VSNK_GATE` | -0.3 | +60.5 | V |
+| `VSNK_GATE` | `VSNK_SRC` - 0.3 | `VSNK_SRC` + 5.5 | V |
+| `VSRC_SRC` | -0.3 | +5.5 | V |
+| `VSRC_BOOT` | -0.3 | +11 | V |
+| `VSRC_BOOT` | `VSRC_SRC` - 0.3 | `VSRC_SRC` + 5.5 | V |
+| `VSRC_GATE` | -0.3 | +11.3 | V |
+| `VSRC_GATE` | `VSRC_SRC` - 0.3 | `VSRC_BOOT` + 0.3 | V |
+| `CC1`, `CC2`, `RD1`, `RD2` | -0.3 | +5.5 | V |
+| `SDA`, `SCL`, `ALERT#`, `OCP#`, `PROCHOT#` | -0.3 | +5.5 | V |
+| `GPIO1`, `GPIO2`, `GPIO3`, `GPIO4` | -0.3 | +3.6 | V |
+| **Ambient Temperature** | | | |
+| Part number:<br>RAA489400ARGNP#HA0<br>RAA489400ARGNP#MA0 | -10 | +100 | °C |
+| Part number:<br>RAA489400A3GNP#HA0<br>RAA489400A3GNP#MA0 | -40 | +105 | °C |
+| Junction Temperature | -10 | +125 | °C |
+
+## 3.3 Thermal Specifications
+
+| Parameter | Package | Symbol | Conditions | Typical Value | Unit |
+| --- | --- | --- | --- | --- | --- |
+| Thermal Resistance | 32 Ld FCQFN Package | θ_JA [1] | Junction to ambient | 40 | °C/W |
+| Thermal Resistance | 32 Ld FCQFN Package | θ_JC [2] | Junction to case | 6 | °C/W |
+
+Notes:
+
+1. θ_JA is measured on JEDEC std. PCB with Direct Attach features including two 100µm dia. vias under pin #4, and two 100µm dia. vias under pin #24. See TB379.
+2. For θ_JC, the case temperature is measured on the package bottom surface at pins #4 and #24.
+
+## 3.4 Electrical Specifications
+
+Recommended operating conditions unless otherwise noted. `VSYS33` = 3.3V, `VCONN_POWER` = 5.0V, and T_A = -40°C to +105°C, unless otherwise specified.
+
+| Parameter | Symbol | Test Conditions | Min [1] | Typ | Max [1] | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| **UVLO/ACOK** | | | | | | |
+| VBUS OK Rising | `VBUS_OK_r` | - | 3.6 | 3.81 | 3.95 | V |
+
+<!-- page 16 -->
+
+**RAA489400 Datasheet**
+
+### Electrical Specifications (continued)
+
+| Parameter | Symbol | Test Conditions | Min [1] | Typ | Max [1] | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| VBUS OK Hysteresis | `VBUS_OK_h` | - | - | 300 | - | mV |
+| VSYS33 OK Rising | `VSYS33OK_r` | - | 2.8 | 2.9 | 3 | V |
+| VSYS33 OK Falling | `VSYS33OK_f` | - | 2.6 | 2.68 | 2.8 | V |
+| VDD25 2P4 POR Rising | `VDD2p5_2P4_r` | SMBus | - | 2.3 | - | V |
+| VDD25 2P4 POR Hysteresis | `VDD2p5_2P4_h` | - | - | 125 | - | mV |
+| VDD33 OK Rising | `VDD2p9OK_r` | - | 2.65 | 2.857 | 3.06 | V |
+| VDD33 OK Hysteresis | `VDD2p9OK_h` | - | - | 100 | - | mV |
+| **Linear Regulator** | | | | | | |
+| VDD25 Output Voltage | `VDD2P5` | 3.0V < `VDD33` < 3.6V, no load | 2.45 | 2.55 | 2.7 | V |
+| VDD25 Dropout Voltage | `VDD2P5_dp` | 10mA, `VDD33` = 2.5V | 44 | 66 | 88 | mV |
+| VDD25 Overvoltage Rising | `VDD2P5_OV_r` | - | - | 3.3 | - | V |
+| VDD25 Overvoltage Hysteresis | - | - | - | 200 | - | mV |
+| VDD33 Output Voltage | `VDD3P3` | 3.8V < `VBUS` < 51V, no load | 3.1 | 3.3 | 3.5 | V |
+| VDD33 Dropout Voltage | `VDD3P3_dp` | 30mA, `VBUS` > 3.8V | - | 25 | - | mV |
+| VDD33 Overcurrent Threshold | `VDD3P3_OC` | - | 25 | 40 | 55 | mA |
+| **Input Current Sense Amplifier, Rs = 10mΩ** | | | | | | |
+| CSIP/CSIN Input Voltage Range | `VCSIP/N` | - | 4 | - | 55 | V |
+| **Fast Role Swap** | | | | | | |
+| VBUS Top Window Comparator Falling Threshold | `vFrsVbus` | Setting 1 (5.2V) | 4.9 | 5.1 | 5.3 | V |
+| VBUS Top Window Comparator Falling Threshold | `vFrsVbus` | Setting 2 (5.5V) | 5.25 | 5.4 | 5.55 | V |
+| VBUS Top Window Comparator Falling Threshold | `vFrsVbus` | Setting 3 (5.8V) | 5.5 | 5.7 | 5.9 | V |
+| VBUS Top Window Comparator Hysteresis | - | - | - | 0.36 | - | V |
+| **Protection** | | | | | | |
+| Over-Temperature Threshold | `tVconn_ot` | - | - | 155 | - | °C |
+| VBUS Overvoltage Rising Threshold (SPR) | `vSprMax` | - | 23 | 23.41 | 24 | V |
+| VBUS Overvoltage Hysteresis (SPR) | `vVbusOvHysSpr` | - | - | 260 | - | mV |
+| VBUS Overvoltage Rising Threshold (EPR) | `vEprMax` | - | 52.6 | 54.0 | 56.2 | V |
+| VBUS Overvoltage Hysteresis (EPR) | `vVbusOvHysEpr` | - | - | 550 | - | mV |
+| SRC VBUS Undervoltage Falling Threshold | `vVbusUv` | - | 3.45 | 3.76 | 4.25 | V |
+| SRC VBUS Undervoltage Hysteresis | - | - | - | 360 | - | mV |
+| SRC 5V VBUS Overvoltage Rising Threshold | `vVbusOv` | - | 5.8 | 6.3 | 6.6 | mV |
+| SRC 5V VBUS Overvoltage Hysteresis | - | - | - | 600 | - | mV |
+| SRC VBUS Reverse Voltage Rising Threshold | `vVbusRv` | V_VBUS – V_CSIN | 20 | - | 100 | mV |
+| SRC VBUS Reverse Voltage Hysteresis | - | - | - | 2 | - | mV |
+
+<!-- page 17 -->
+
+**RAA489400 Datasheet**
+
+### Electrical Specifications (continued)
+
+| Parameter | Symbol | Test Conditions | Min [1] | Typ | Max [1] | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| VBUS Overcurrent Rising Threshold | `iVbusOc` | Setting 1 (1.5A) | 1.65 | - | 1.88 | A |
+| VBUS Overcurrent Rising Threshold | `iVbusOc` | Setting 2 (3A) | 3.3 | - | 3.6 | A |
+| VBUS Overcurrent Rising Threshold | `iVbusOc` | Setting 3 (4A) | 4.4 | - | 4.8 | A |
+| VBUS Overcurrent Rising Threshold | `iVbusOc` | Setting 4 (5A) | 5.5 | - | 6.0 | A |
+| VBUS Overcurrent Hysteresis | `iVbusOcHys` | - | - | 400 | - | mA |
+| VCONN Overvoltage Rising Threshold | `vVconnOv` | - | 5.8 | 6.26 | 6.6 | V |
+| VCONN Overvoltage Hysteresis | `vVconnOvHys` | - | - | 500 | - | mV |
+| VCONN Undervoltage Falling Threshold | `vVconnUv` | - | 3.45 | 3.79 | 4.25 | V |
+| VCONN Undervoltage Hysteresis | `vVconnUvHys` | - | 170 | 210 | 320 | mV |
+| VCONN Reverse Voltage Rising Threshold | `vVconnRv` | V_CC1/CC2 – VCONN | 250 | 325 | 500 | mV |
+| VCONN Reverse Voltage Hysteresis | `vVconnRvHys` | - | - | 100 | - | mV |
+| VCONN Overcurrent Rising Threshold | `iVconnOc` | Setting 1 (400mA) | 400 | - | 600 | mA |
+| VCONN Overcurrent Rising Threshold | `iVconnOc` | Setting 2 (600mA) | 600 | - | 800 | mA |
+| VCONN Overcurrent Rising Threshold | `iVconnOc` | Setting 3 (800mA) | 800 | - | 1050 | mA |
+| VCONN OC Blanking Time [2] | `tVconnOcBlnk` | - | - | 5 | - | ms |
+| **Oscillator** | | | | | | |
+| 24MHz Oscillator Frequency, Digital Core Only | - | - | - | 24 | - | MHz |
+| 3MHz Oscillator Frequency | - | - | - | 3 | - | MHz |
+| Digital Debounce Time Accuracy [2] | - | - | -15 | - | 15 | % |
+| 30kHz Oscillator Frequency | - | - | - | 30 | - | kHz |
+| **Charge Pump Gate Drivers** | | | | | | |
+| VBUS Source Gate Vgs | - | `VSRC_GATE` - `VSRC_SRC` | 4.2 | 4.4 | 4.6 | V |
+| VBUS Sink Gate Vgs | - | `VSNK_GATE` - `VSNK_SRC` | 4.5 | 5.1 | 5.5 | V |
+| Charge Pump Startup Time | `tCpStart` [2] | - | - | - | 50 | ms |
+| **VBUS** | | | | | | |
+| VBUS ADC Accuracy | - | `VBUS` > 2.8V — VBUS Voltage | -2 | - | +2 | % |
+| VBUS ADC Accuracy | - | 2.0V ≤ `VBUS` ≤ 2.8V — VBUS Voltage | -50 | - | +50 | mV |
+| VBUS ADC Accuracy | - | `VBUS` < 2.0V — VBUS Voltage | -75 | - | +75 | mV |
+| VBUS ADC Accuracy | - | `VBUS` > 600mA — VBUS Current | -5 | - | +5 | % |
+| VBUS ADC Accuracy | - | `VBUS` = 500mA — VBUS Current | - | 498 | - | mA |
+| VBUS ADC Accuracy | - | `VBUS` = 200mA — VBUS Current | - | 197 | - | mA |
+| VBUS ADC Accuracy | - | `VBUS` = 100mA — VBUS Current | - | 104 | - | mA |
+| SNK VBUS Disconnect Detect DAC Accuracy | - | 11-bit DAC, LSB = 25mV, VBUS Voltage > 0.5V | -5 | - | +5 | % |
+
+<!-- page 18 -->
+
+**RAA489400 Datasheet**
+
+### Electrical Specifications (continued)
+
+| Parameter | Symbol | Test Conditions | Min [1] | Typ | Max [1] | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| **VCONN Mux** | | | | | | |
+| VCONN Switch Rdson | - | - | - | 500 | - | mΩ |
+| VCONN Switch Turn on Time [2] | - | Time from enable to fully on, with 10µF cap | - | - | 1.5 | ms |
+| VCONN Discharge Stop Voltage | `vVconnDischarge` | - | - | - | 0.8 | V |
+| VCONN Discharge Time [2] | `tVconnZero` | - | - | - | 100 | ms |
+| **CCx Discharge** | | | | | | |
+| VCONN Mux Discharge Rdson | `Rdch` | - | - | 100 | - | Ω |
+| **Cable Settings** | | | | | | |
+| Rd Clamp | - | - | 0.8 | 1.1 | 1.3 | V |
+| Rd Resistor | - | - | 4.59 | 5.1 | 5.61 | kΩ |
+| IP Current | - | Default USB Power | 64 | 80 | 96 | µA |
+| IP Current | - | 1.5A at 5V | 166 | 180 | 194 | µA |
+| IP Current | - | 3A at 5V | 304 | 330 | 356 | µA |
+| **TX** | | | | | | |
+| Bit Rate | `fBitRate` | - | 270 | 300 | 330 | Kps |
+| Fall Time | `tFall` | 10% and 90% amplitude points, minimum is under an unload condition | 300 | - | - | ns |
+| Rise Time | `tRise` | 10% and 90% amplitude points, minimum is under an unload condition | 300 | - | - | ns |
+| Voltage Swing | `vSwing` | Applies to both no load condition and under the load condition specified in USB-PD Spec | 1.05 | - | 1.2 | V |
+| Output Impedance | `zDrive` | Source output impedance at the Nyquist frequency of [USB 2.0] low speed (750kHz) while the source is driving the CC line. | 33 | - | 75 | Ω |
+| **SMBus/I²C, GPIO** | | | | | | |
+| `SDA`/`SCL`, `GPIO1/2/3/4` Input Low Voltage | `VIL` | - | - | - | 0.5 | V |
+| `SDA`/`SCL`, `GPIO1/2/3/4` Input High Voltage | `VIH` | - | 1.2 | - | - | V |
+| `SDA`/`SCL`, `GPIO1/2/3/4` Input Bias Current | - | - | - | - | 1 | µA |
+| SDA Output Sink Current | `IOL_SDA` | V_SDA = 0.4V, on | 11 | - | - | mA |
+| SMBus/I²C Frequency | `fSMB` | - | 10 | - | 1000 | kHz |
+| `ALERT#`, `OCP#`, `PROCHOT#`, `GPIO1/2/3/4` Input Leakage Current | - | - | - | - | 1 | µA |
+| `ALERT#`, `OCP#`, `PROCHOT#`, `GPIO1/2/3/4` Output Sink Current | `IOL GPIO` | GPIO Voltage = 0.4V | 4 | - | - | mA |
+| `GPIO1/2/3/4` Output Source Current | `IOH_GPIO` | - | 4 | - | - | mA |
+
+<!-- page 19 -->
+
+**RAA489400 Datasheet**
+
+### Electrical Specifications (continued)
+
+| Parameter | Symbol | Test Conditions | Min [1] | Typ | Max [1] | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| `ALERT#`, `OCP#`, `PROCHOT#`, `GPIO1/2/3/4` Output Low Voltage | `VOL` | - | - | - | 0.4 | V |
+| `GPIO1/2/3/4` Output High Voltage | `VOH` | - | 2.4 | - | - | V |
+
+Notes:
+
+1. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
+2. Limits established by characterization are not production tested.
+
+## 3.5 SMBus Timing Specification
+
+| Parameter | Symbol | Test Conditions | Min [1] | Typ | Max [1] | Unit |
+| --- | --- | --- | --- | --- | --- | --- |
+| Bus Free Time [2] | t_BUF | - | 0.5 | - | - | µs |
+| Start Condition Hold Time from SCL [2] | t_HD:STA | - | 0.26 | - | - | µs |
+| Start Condition Set-Up Time from SCL [2] | t_SU:STA | - | 0.26 | - | - | µs |
+| Stop Condition Set-Up Time from SCL [2] | t_SU:STO | - | 0.26 | - | - | µs |
+| SDA Hold Time from SCL [2] | t_HD:DAT | - | 0 | - | - | ns |
+| SDA Set-Up Time from SCL [2] | t_SU:DAT | - | 50 | - | - | ns |
+| SCL Low Period [2] | t_LOW | - | 0.5 | - | - | µs |
+| SCL High Period [2] | t_HIGH | - | 0.26 | - | 50 | µs |
+
+Notes:
+
+1. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.
+2. Limits established by characterization are not production tested.

REN_RAA489400/04-typical-performance-graphs.md

@@ -0,0 +1,22 @@
+<!-- page 20 -->
+
+RAA489400 Datasheet
+
+# 4. Typical Performance Graphs
+
+**Figure 11. Startup VSYS33 Powered (2.0ms/Div, 2.0V/Div)**
+
+![Figure 11. Startup VSYS33 Powered (2.0ms/Div, 2.0V/Div)](04-typical-performance-graphs/figure-11.png)
+
+**Figure 12. Startup from VBUS (2.0ms/Div on C1 = VSYS33, C2 = VDD25, C4 = ALERT#, 10V/Div on C3 = VBUS**
+
+![Figure 12. Startup from VBUS (2.0ms/Div on C1 = VSYS33, C2 = VDD25, C4 = ALERT#, 10V/Div on C3 = VBUS](04-typical-performance-graphs/figure-12.png)
+
+---
+
+R16DS0292EU0100  Rev.1.00
+Aug 27, 2024
+
+RENESAS
+
+Page 20

REN_RAA489400/05-functional-description.md

@@ -0,0 +1,380 @@
+<!-- page 21 -->
+
+# 5. Functional Description
+
+## 5.1 Start-Up
+
+When `VSYS33` is supplied, 3.3V is supplied to a 3.3V domain block, `VSNK_GATE`/`VSNK_SRC` gate driver, and 2.5V LDO. Also, `VSYS33` is passed through `VDD33`. In this condition, the 3.3V LDO is disabled.
+
+When `VSYS33` is not supplied and `VBUS` is supplied, `VBUS` is the input to the 3.3V LDO and the `VSYS33` switch (VSYS33 SW) is turned off. Also, the 3.3V LDO outputs 3.3V to the 3.3V domain block, `VSNK_GATE`/`VSNK_SRC` gate driver, 2.5V LDO, and `VDD33`. This condition is implemented for when the system does not have any power (for example, dead battery condition).
+
+When the output of the 2.5V LDO rises above a 2.4V POR threshold (`VDD2p5_2P4_r`), the RAA489400 digital block is activated and starts the TCPC operation.
+
+When `VDD33` is supplied but both `VSYS33` and `VBUS` are not supplied, 2.5V LDO is not enabled and the RAA489400 does not start the TCPC operation.
+
+When `VCONN_POWER` is supplied, 5V is supplied to VCONN Mux, charge pump for VCONN, and charge pump for `VSRC_GATE`/`VSRC_SRC`/`VSRC_BOOT`.
+
+## 5.2 Programming Resistors
+
+A 1% resistor from the `PROG` pin to GND programs the configuration of the RAA489400.
+
+Table 1 shows the programming option for the SMBus/I²C slave target address. When `VDD33` is powered from either `VSYS33` or `VBUS`, RAA489400 checks the resistance value that is connected to `PROG` pin with GND, and it configures the SMBus/I²C slave target address based on Table 1.
+
+If the RAA489400 receives I²C access before completing a read to the `PROG` resistor, the RAA489400 ignores the I²C access.
+
+**Table 1. PROG Pin Programming Table**
+
+| PROG-GND Resistance (Ω) — Min | PROG-GND Resistance (Ω) — Nominal | PROG-GND Resistance (Ω) — Max | Slave Target Address (7-bit) |
+| --- | --- | --- | --- |
+| 950 | 1000 | 1050 | 0x22 |
+| 1425 | 1500 | 1575 | 0x23 |
+| 2090 | 2200 | 2310 | 0x24 |
+| 3135 | 3300 | 3465 | 0x25 |
+| 4465 | 4700 | 4935 | 0x26 |
+| 6460 | 6800 | 7140 | 0x27 |
+
+## 5.3 USB Type-C Port Controller Interface
+
+The RAA489400 supports USB Type-C Port Controller Interface specification Revision 2.0 with EPR, which is defined in USB PD specification Revision 3.1. TCPM controls RAA489400 USB Type-C Port Controller through the SMBus/I²C slave target register. Reference the Registers section for details on the TCPC standard and the RAA489400 vendor-defined register information.
+
+### 5.3.1 USB PD BMC PHY
+
+The RAA489400 supports USB PD BMC (Bi-phase Mark coded) Baseband PHY. The TCPM enables the USB PD BMC PHY when the RAA489400 is in Attached.SNK, Attach.SRC, DebugAccessory with either Source only, Sink only, or the DRP (Dual Role Power) power role, which is configured in `ROLE_CONTROL (1Ah)`. The
+
+<!-- page 22 -->
+
+`RECEIVE_BUFFER (30h)` and `TRANSMIT_BUFFER (50h)` registers are supported to transmit/receive USB PD protocol messages.
+
+### 5.3.2 USB Type-C Current Mode
+
+The RAA489400 supports the following USB Type-C current options: Default, 1.5A, or 3.0A. This configuration is set in `ROLE_CONTROL (1Ah)`.
+
+### 5.3.3 VCONN Mux
+
+The VCONN source mux provides 5V power from the `VCONN_POWER` pin to `CC1` or `CC2` when `Bit0.Enable VCONN` in `POWER_CONTROL (1Ch)` is set to 1b. `Bit0.Plug Orientation` in `TCPC_CONTROL (19h)` must be configured for plug orientation when the USB-C device is connected.
+
+When the VCONN fault protection (OV/UV/OT/RV) is enabled and a fault condition is detected, the RAA489400 turns off VCONN Mux.
+
+5V is supplied to `VCONN_POWER` when the RAA489400 works as a VBUS source.
+
+### 5.3.4 Source Path Control
+
+RAA489400 supports two options for VBUS source path control. The following options are configured in `GPIO1_CTRL Register (82h)`, `GPIO2_CTRL Register (83h)`, `GPIO3_CTRL Register (84h)`, `GPIO4_CTRL Register (85h)`, `VBUS_PATH_CTRL Register (86h)`, and `VBUS_GPIO_CTRL Register (87h)`.
+
+- `VSRC_GATE`/`VSRC_SRC`/`VSRC_BOOT` for external N-ch MOSFET
+- GPIO (VBUS source power switch enable function for external VBUS power switch)
+
+When TCPM sends a command of DisableSourceVbus or SourceVbusDefaultVoltage to the RAA489400 through `COMMAND (23h)`, the RAA489400 turns off/on the VBUS source path.
+
+When the VBUS source fault protection (OC/OV/UV/RV) is enabled and a fault condition is detected, RAA489400 turns the VBUS source path off.
+
+### 5.3.5 Sink Path Control
+
+The RAA489400 supports two options for the VBUS sink path control. The following options are configured in `GPIO1_CTRL Register (82h)`, `GPIO2_CTRL Register (83h)`, `GPIO3_CTRL Register (84h)`, `GPIO4_CTRL Register (85h)`, `VBUS_PATH_CTRL Register (86h)`, and `VBUS_GPIO_CTRL Register (87h)`.
+
+- `VSNK_GATE`/`VSNK_SRC` for external N-ch MOSFET
+- GPIO (VBUS sink power switch enable function for external VBUS power switch)
+
+When the TCPM sends a command of DisableSinkVbus or SinkVbus to the RAA489400 through `COMMAND (23h)`, the RAA489400 turns off/on the VBUS sink path.
+
+When the VBUS sink fault protection (OV/UV) is enabled and a fault condition is detected, the RAA489400 turns off VBUS sink path.
+
+### 5.3.6 Bi-directional VBUS Source and Sink Path Control
+
+The RAA489400 supports one option for a bi-directional VBUS source and sink path control (see Figure 9). The GPIO must be used to control the bi-directional VBUS source and sink path. `VBUS_SRC_SEL` and `VBUS_SNK_SEL` must be set with same value with one GPIO pin in `VBUS_PATH_CTRL Register`.
+
+For example, `VBUS_PATH_CTRL Register` is set to 0x33 with `GPIO1`. In this case, when the TCPM sends a command of SourceVbusDefaultVoltage or SinkVbus to RAA489400, `GPIO1` is asserted to turn bi-directional VBUS source and sink path on. When the TCPM sends a command of DisableSourceVbus and DisableSinkVbus to the RAA489400, `GPIO1` is deasserted to turn bi-directional VBUS source and sink path off. Because of VBUS protection functions, the TCPM must send an appropriate command to control that is based on `CC_STATUS Register`.
+
+<!-- page 23 -->
+
+*Note*: `SRC_VBUS_RVP_DIS` must be set to 1b to disable the VBUS reverse voltage protection function when `VBUS_SRC_SEL` and `VBUS_SNK_SEL` are set to same value for bi-directional VBUS path control.
+
+### 5.3.7 VBUS Monitoring and Measurement
+
+The RAA489400 supports the VBUS Monitoring and Measurement function for VBUS voltage, VBUS current, Sink Disconnect Detection, and VBUS Discharge to vSafe0V as described in the following sections.
+
+#### 5.3.7.1 VBUS Voltage Measurement
+
+The TCPM can monitor the VBUS voltage measurement status in `VBUS_VOLTAGE (70h)` when `Bit6.VBUS_VOLTAGE Monitor` in `POWER_CONTROL (1Ch)` is enabled.
+
+#### 5.3.7.2 VBUS Current Measurement
+
+The TCPM can monitor VBUS current measurement status in `VBUS_CURRENT Register (92h)` when the Disabled `VBUS_CURRENT` monitor is set to 0b in `VBUS_CTRL Register (90h)`.
+
+The TCPM can also monitor a peak current and average current in `VBUS_PEAK_CURRENT Register (94h)` and `VBUS_AVE_CURRENT Register (96h)` when `Bit4.PEAK_EN` and/or `Bit7.AVERAGE_EN` is enabled in `VBUS_CTRL Register (90h)`.
+
+`VBUS_PEAK_CURRENT Register (94h)` shows a maximum VBUS peak current.
+
+`VBUS_AVE_CURRENT Register (96h)` shows an average current over a time period specified in `VBUS_CTRL Register (90h)`. The RAA489400 calculates the average current as the following. Refer to `VBUS_CTRL Register (90h)` for more information.
+
+$$y_n = \text{Average Current at Time } n,\quad x_n = \text{VBUS Current sampled at Time } n,\quad y_0 = 0$$
+
+$$y_{n+1} = y_n + \frac{(x_n - y_n)}{(N3 \times 2^{N4})}$$
+
+#### 5.3.7.3 VBUS Voltage Alarm
+
+The VBUS voltage alarm function is disabled as a default setting per TCPCi specification. The TCPM can write `DisableVoltageAlarms` = 0b in `POWER_CONTROL (1Ch)` to enable the voltage alarms.
+
+The TCPM can write to `VBUS_VOLTAGE_ALARM_HI_CFG (76h)` to set the high voltage alarm level. The RAA489400 sets `VBUSVoltageAlarmHi` to 1b in `ALERT (10h)` when VBUS exceeds the high voltage alarm level in `VBUS_VOLTAGE_ALARM_HI_CFG (76h)`. The RAA489400 re-asserts `VBUSVoltageAlarmHi` in `ALERT (10h)` when the high voltage condition on VBUS prevails after the TCPM has cleared `VBUSVoltageAlarmHi` in `ALERT (10h)` unless the TCPM disables the voltage alarms by setting `DisableVoltageAlarms` to 1b in `POWER_CONTROL (1Ch)`.
+
+The TCPM can write to `VBUS_VOLTAGE_ALARM_LO_CFG (78h)` to set the low voltage alarm level. The RAA489400 sets `VBUSVoltageAlarmLo` to 1 in `ALERT (10h)` when VBUS drops below the low voltage alarm level in `VBUS_VOLTAGE_ALARM_LO_CFG (78h)`. The RAA489400 re-asserts `VBUSVoltageAlarmLo` in `ALERT (10h)` when the low voltage condition on VBUS prevails after the TCPM has cleared `VBUSVoltageAlarmLo` in `ALERT (10h)`, unless the TCPM disables the voltage alarms by setting `DisableVoltageAlarms` to 1b in `POWER_CONTROL (1Ch)`.
+
+#### 5.3.7.4 VBUS Discharge
+
+The RAA489400 supports the automatic VBUS discharge function after a disconnect detection when `Bit4.Auto Discharge Disconnect` is set to 1b in `POWER_CONTROL (1Ch)` 1b. The RAA489400 supports force VBUS discharge by setting `Bit.2.Force Discharge` in `POWER_CONTROL (1Ch)` so that the TCPM can manually discharge VBUS.
+
+When the RAA489400 starts the VBUS discharge to vSafe0V, the RAA489400 monitors the VBUS voltage and stops the VBUS discharge when VBUS is below vSafe0V (max). When the VBUS discharge is stopped, the RAA489400 does not reapply the VBUS discharge although the VBUS might be higher than vSafe0V (max), but it does reapply the VBUS discharge when another VBUS discharge command or event occurs.
+
+<!-- page 24 -->
+
+In contrast, when the RAA489400 is the source and the `Force Discharge` bit of the `POWER_CONTROL` register is set to 1b, the RAA489400 starts the VBUS discharge and monitors the VBUS voltage to stop the discharging. The discharging VBUS voltage is stopped when the VBUS voltage is below the `VBUS_STOP_DISCHARGE_THRESHOLD` register.
+
+### 5.3.8 Internal Sink Path Discharge
+
+The RAA489400 provides an internal Sink discharge function with the `SNK_DISCHG` pin to discharge an internal sink path, for example, between VBUS sink gate and the battery charger (adapter side).
+
+When a system supports multiple USB-C ports with multiple RAA489400 devices and the first USB-C port (C1) has an EPR Source adapter (up to 240W/48V) and a second USB-C port (C2) has a SPR (up to 100W/20V) source adapter (as in Figure 13), the internal system sink path between the VBUS sink gate and a battery charger (adapter side) has a high voltage (such as 48V). In this case when the EPR source adapter is disconnected, the internal system sink path must be discharged to vSafe5V or 0V for safety before the VBUS sink gate of the second USB-C port is turned on. Otherwise, the SPR source adapter on the second USB-C port might have damage because of a higher voltage than its source capability from the internal sink path.
+
+![Figure 13. Typical Multiport Sink Only](05-functional-description/figure-13.png)
+
+The RAA489400 provides the following option for the TCPM or system when the RAA489400 works as a sink. The following options can be configured in `SINK_PATH_DISCHG Register (9Ah)`.
+
+- Automatic discharge when RAA489400 receives SinkVbus command.
+- Manual discharge with TCPM operation.
+
+#### 5.3.8.1 Automatic Discharge
+
+When `DISCHG_MODE` of `SINK_PATH_DISCHG Register (9Ah)` is set to 1b (that is automatic discharge), the RAA489400 receives the SinkVbus command and the internal sink path voltage exceeds the vSafe5V(max); the RAA489400 automatically discharges the internal sink path voltage until the voltage reaches below the
+
+<!-- page 25 -->
+
+vSafe5V(max). When a voltage is lower than the vSafe5V(max), the RAA489400 stops to discharge and enables VBUS sink gate.
+
+The sink discharge timeout is set to `DISCHARGE_TIMEOUT` of `SINK_PATH_DISCHG Register (9Ah)` if the internal sink path voltage is higher than the vSafe5V(max) after the sink discharge timeout setting of receiving the SinkVbus command. Next, the RAA489400 sets a 1b sink path discharge completion bit (Bit 14) and a Sink path discharge timeout bit (Bit15) of `VENDOR_STATUS Register (A0h)` to notify a discharge failure, and it asserts an `ALERT#` pin to the TCPM. Afterwards, the RAA489400 discards the SinkVbus command. Also, the TCPM can acknowledge the internal sink path has failed to reach the vSafe5V and can report this failure to the EC and/or CPU.
+
+*Note:* The RAA489400 does not discharge the internal sink path when it detects a disconnection.
+
+#### 5.3.8.2 Manual Discharge
+
+When `DISCHG_MODE` of `SINK_PATH_DISCHG Register (9Ah)` is set to 0b (that is manual discharge) and the TCPM writes 1b to `MANUAL_DISCHG` of `SINK_PATH_DISCHG Register (9Ah)`, the RAA489400 discharges the internal sink path voltage to vSafe5V(max). When a voltage is lower than the vSafe5V(max), the RAA489400 stops discharge and sets 1b to the sink path discharge completion bit (Bit14) of `VENDOR_STATUS Register (A0h)` to notify discharge completion and assert `ALERT#` pin to the TCPM. Next, the TCPM can send the SinkVbus command to the RAA489400 that controls the second USB-C port.
+
+The Sink Discharge Timeout of discharge is set to `DISCHARGE_TIMEOUT` of `SINK_PATH_DISCHG Register (9Ah)` if the internal sink path voltage is higher than the vSafe5V(max) after the sink discharge timeout setting of receiving the `MANUAL_DISCHG` = 1b, and the RAA489400 sets 1b to the sink path discharge completion bit (Bit14) and sink path discharge timeout bit (Bit15) of `VENDOR_STATUS Register (A0h)` to notify discharge failure and assert the `ALERT#` pin to TCPM. Finally, the TCPM can acknowledge the internal sink path has failed to reach the threshold setting and can report this failure to the EC and/or CPU.
+
+### 5.3.9 Initial Sink Fast Role Swap
+
+The RAA489400 supports Initial Sink Fast Role Swap based on the USB PD specification. Fast Role Swap can be enabled in `POWER_CONTROL (1Ch)`.
+
+The RAA489400 turns Sink gate off at first when Fast Role Swap occurs, that is when the RAA489400 receives the Fast Role Swap Signal from a connected USB-C/PD VBUS source device. Next, the RAA489400 turns Source gate on for a new sink device.
+
+Trigger conditions of Sink/Source gate control and timing between those controls are defined in `FRS_CTRL Register (98h)`. Settings of this register are valid only when the Fast Role Swap Enable bit of the `POWER_CONTROL (1Ch)` is set to 1b.
+
+The TCPM must disable the Fast Role Swap in `POWER_CONTROL (1Ch)` before the TCPM sends a FR_Swap message.
+
+*Note:* The RAA489400 does not support Initial Source Fast Role Swap.
+
+*Note:* The RAA489400 does not consider Fast Role Swap support with Bi-directional VBUS Source and Sink Path Control.
+
+## 5.4 Protection Features
+
+The RAA489400 supports features for VBUS protection and VCONN Mux protection as described in the following sections. Table 2 and Table 3 clarify the control/status/mask register for each protection.
+
+<!-- page 26 -->
+
+**Table 2. VBUS Protection**
+
+| Protection | Supported Power Role | Control Register | Status Register | Mask Register |
+| --- | --- | --- | --- | --- |
+| VBUS Overcurrent | Source/Sink | `FAULT_CONTROL (1Bh)` | `FAULT_STATUS (1Fh)` | `FAULT_STATUS_MASK (15h)` |
+| VBUS Overvoltage | Source/Sink | `FAULT_CONTROL (1Bh)`<br>`VBUS_FAULT_CTRL Register (A4h)` | `FAULT_STATUS (1Fh)` | `FAULT_STATUS_MASK (15h)` |
+| VBUS Undervoltage | Source | `VBUS_FAULT_CTRL Register (A4h)` | `VENDOR_STATUS Register (A0h)` | `VENDOR_STATUS_ALERT_MASK Register (A2h)` |
+| VBUS Reverse Voltage | Source | `VBUS_FAULT_CTRL Register (A4h)` | `VENDOR_STATUS Register (A0h)` | `VENDOR_STATUS_ALERT_MASK Register (A2h)` |
+
+**Table 3. VCONN Protection**
+
+| Protection | Control Register | Status Register | Mask Register |
+| --- | --- | --- | --- |
+| VCONN Overcurrent | `FAULT_CONTROL (1Bh)`<br>`VCONN_FAULT_CTRL Register (A6h)` | `FAULT_STATUS (1Fh)` | `FAULT_STATUS_MASK (15h)` |
+| VCONN Overvoltage | `VCONN_FAULT_CTRL Register (A6h)` | `VENDOR_STATUS Register (A0h)` | `VENDOR_STATUS_ALERT_MASK Register (A2h)` |
+| VCONN Undervoltage | `VCONN_FAULT_CTRL Register (A6h)` | `VENDOR_STATUS Register (A0h)` | `VENDOR_STATUS_ALERT_MASK Register (A2h)` |
+| VCONN Reverse Voltage | `VCONN_FAULT_CTRL Register (A6h)` | `VENDOR_STATUS Register (A0h)` | `VENDOR_STATUS_ALERT_MASK Register (A2h)` |
+| VCONN Over-temperature | `VCONN_FAULT_CTRL Register (A6h)` | `VENDOR_STATUS Register (A0h)` | `VENDOR_STATUS_ALERT_MASK Register (A2h)` |
+
+### 5.4.1 VBUS Overcurrent Protection
+
+If the VBUS Overcurrent Protection Fault is enabled in `FAULT_CONTROL (1Bh)`, the RAA489400 takes the following actions when the VBUS overcurrent is detected either internally with `CSIP`/`CSIN` or externally with the overcurrent input from the GPIO function.
+
+- Turns off the VBUS source gate and discharge VBUS to vSafe0V when the RAA489400 works as a VBUS source.
+- Turns off the VBUS sink gate when the RAA489400 works as a VBUS sink.
+- Sets the VBUS Overcurrent Protection Fault bit in `FAULT_STATUS (1Fh)`.
+- Asserts the `OCP#` pin if `VBUS_OCP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+- If the RAA489400 works as a VCONN source (that is Enable VCONN = 1b in `POWER_CONTROL (1Ch)`), the RAA489400 also takes the following actions:
+  - Turns off VCONN Mux and discharges VCONN to vVconnDischarge.
+  - Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`.
+
+The VBUS overcurrent threshold can be configured in `VBUS_FAULT_CTRL Register (A4h)`. The following threshold setting is available: 3.6A (Default), 1.8A, 4.8V, and 6.0A.
+
+<!-- page 27 -->
+
+### 5.4.2 VBUS Overvoltage Protection
+
+If the VBUS Overvoltage Protection Fault is enabled in `FAULT_CONTROL (1Bh)` and/or `VBUS_FAULT_CTRL Register (A4h)`, the RAA489400 takes the following actions when VBUS overvoltage is detected.
+
+- Turns off the VBUS source gate and discharges VBUS to vSafe0V when the RAA489400 works as a VBUS source
+- Turn off the VBUS sink gate when the RAA489400 works as a VBUS sink.
+- Sets the VBUS Overvoltage Protection Fault bit in `FAULT_STATUS (1Fh)`.
+- Asserts the `OCP#` pin if the `VBUS_OVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+- If RAA489400 works as VCONN source (that is Enable VCONN = 1b in `POWER_CONTROL (1Ch)`), the RAA489400 also takes the following actions:
+  - Turns off VCONN Mux and discharges VCONN to vVconnDischarge.
+  - Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`.
+
+*Note:* The VBUS source overvoltage thresholds are vVbusOv, vSprMax, or vEprMax in the Electrical Specifications. The VBUS sink overvoltage thresholds are vSprMax or vEprMax in the Electrical Specifications. The VBUS overvoltage threshold is configured in `VBUS_FAULT_CTRL Register (A4h)`.
+
+### 5.4.3 VBUS Source Undervoltage Protection
+
+If VBUS Source Undervoltage Protection is enabled in the `VBUS_FAULT_CTRL Register (A4h)`, the RAA489400 takes the following when VBUS source undervoltage is detected and RAA489400 works as a VBUS Source.
+
+- Turns off the VBUS source gate and discharges VBUS to vSafe0V.
+- Sets `SRC_VBUS_UVP` bit in `VENDOR_STATUS Register (A0h)`.
+- Asserts the `OCP#` pin if `SRC_VBUS_UVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+- Sets the VBUS Overcurrent Protection Fault bit in `FAULT_STATUS (1Fh)` if the VBUS Overcurrent Protection Fault bit in `FAULT_CONTROL (1Bh)` is set to 0b and `VBUS_UVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+- If the RAA489400 works as a VCONN source (that is Enable VCONN = 1b in `POWER_CONTROL (1Ch)`), the RAA489400 also takes the following actions:
+  - Turns off VCONN Mux and discharges VCONN to vVconnDischarge.
+  - Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`.
+
+*Note:* The VBUS source undervoltage detection is not activated from the moment VBUS is enabled to the time specified by `UVP_INACTIVE_TIME` is elapsed, although the `SRC_VBUS_UVP_DIS` bit of `VBUS_FAULT_CTRL Register (A4h)` is 0b and the VBUS voltage is below the vVbusUv threshold.
+
+*Note:* The RAA489400 does not support the VBUS sink undervoltage when the RAA489400 works as a VBUS sink, because the RAA489400 supports `VBUS_SINK_DISCONNECT_THRESHOLD (72h)` to detect a disconnection.
+
+### 5.4.4 VBUS Source Reverse Voltage Protection
+
+If VBUS Source Reverse Voltage Protection is enabled in `VBUS_FAULT_CTRL Register (A4h)`, the RAA489400 takes the following when VBUS RV is detected.
+
+- Turns off VBUS source gate and then discharges VBUS to vSafe0V when the RAA489400 works as a VBUS source.
+- Sets the `SRC_VBUS_RVP` bit in `VENDOR_STATUS Register (A0h)`.
+- Asserts the `OCP#` pin if `VBUS_RVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+- Sets the VBUS Overcurrent Protection Fault bit in `FAULT_STATUS (1Fh)`, if the VBUS Overcurrent Protection is enabled in `FAULT_CONTROL (1Bh)` and `VBUS_RVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+
+<!-- page 28 -->
+
+- If the RAA489400 works as a VCONN source (that is Enable VCONN = 1b in `POWER_CONTROL (1Ch)`), the RAA489400 also takes the following actions:
+  - Turns off VCONN Mux and discharges VCONN to vVconnDischarge.
+  - Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`.
+
+*Note*: When `VBUS_SRC_SEL` and `VBUS_SNK_SEL` are set to the same value in `VBUS_PATH_CTRL Register` for bi-directional VBUS path control, the VBUS source reverse voltage protection must be disabled.
+
+### 5.4.5 VCONN Overcurrent Protection
+
+If the VCONN Overcurrent Fault is enabled in `FAULT_CONTROL (1Bh)`, the RAA489400 takes the following when the VCONN Overcurrent is detected.
+
+- Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`.
+- Turns off VCONN Mux and discharges VCONN to vVconnDischarge.
+- Sets the VCONN Overcurrent Fault bit in `FAULT_STATUS (1Fh)`.
+- Asserts the `OCP#` pin if `VCONN_OCP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+
+The VCONN overcurrent threshold is configured in the `VCONN_FAULT_CTRL Register (A6h)`. The following threshold setting is available: 400mA (default), 600mA, and 800mA.
+
+### 5.4.6 VCONN Overvoltage Protection
+
+The RAA489400 takes the following when VCONN overvoltage is detected.
+
+- Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`.
+- Turns off VCONN Mux and discharges VCONN to vVconnDischarge.
+- Sets the `VCONN_OVP` bit in `VENDOR_STATUS Register (A0h)`.
+- Asserts the `OCP#` pin if `VCONN_OVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+- Sets the VCONN Overcurrent Fault in `FAULT_STATUS` Register, if the VCONN Overcurrent Fault is enabled in `FAULT_CONTROL (1Bh)` and `VCONN_OVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+
+### 5.4.7 VCONN Undervoltage Protection
+
+The RAA489400 takes the following when VCONN UV is detected.
+
+- Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`.
+- Turns off the VCONN Mux and discharges VCONN to vVconnDischarge.
+- Sets the `VCONN_UVP` bit in `VENDOR_STATUS Register (A0h)`.
+- Asserts the `OCP#` pin if `VCONN_UVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+- Sets the VCONN Overcurrent Fault bit in `FAULT_STATUS (1Fh)`, if the VCONN Overcurrent Fault is enabled in `FAULT_CONTROL (1Bh)` and `VCONN_UVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+
+*Note:* `VCONN_UV` detection is not activated from the moment VCONN is enabled to the time specified by `UVP_INACTIVE_TIME` of `VCONN_FAULT_CTRL Register (A6h)` is elapsed, although, `VCONN_UVP_DIS` bit of `VCONN_FAULT_CTRL Register (A6h)` is 0b and VCONN voltage is below the vVconnUv threshold.
+
+### 5.4.8 VCONN Over-temperature Protection
+
+If the VCONN Overtemperature Fault is enabled in `VCONN_FAULT_CTRL Register (A6h)`, the RAA489400 takes the following when VCONN OT is detected.
+
+- Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`.
+- Turns off VCONN Mux and discharges VCONN to vVconnDischarge.
+- Turns off the VBUS source gate and discharges VBUS to vSafe0V when the RAA489400 works as a VBUS source.
+- Turns off the VBUS sink gate when the RAA489400 works as a VBUS sink.
+
+<!-- page 29 -->
+
+- Sets the `VCONN_OTP` bit in `VENDOR_STATUS Register (A0h)`.
+- Asserts the `OCP#` pin if `VCONN_OTP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+
+### 5.4.9 VCONN Reverse Voltage Protection
+
+RAA489400 takes the following when VCONN RV is detected.
+
+- Clears Enable VCONN to 0b in `POWER_CONTROL (1Ch)`
+- Turns off VCONN Mux and then discharge VCONN to vVconnDischarge.
+- Turns off VBUS source gate and then discharge VBUS to vSafe0V when RAA489400 works as VBUS source.
+- Turns off VBUS sink gate when RAA489400 works as VBUS sink.
+- Sets `VCONN_RVP` bit in `VENDOR_STATUS Register (A0h)`.
+- Asserts `OCP#` pin if `VCONN_RVP` of is set to 1b.
+- Sets the VCONN Overcurrent Fault bit in `FAULT_STATUS (1Fh)`, if the VCONN Overcurrent Fault is enabled in `FAULT_CONTROL (1Bh)` and `VCONN_RVP` of `OCP_OUTPUT_CTRL Register (A8h)` is set to 1b.
+
+## 5.5 OCP# Output
+
+When RAA489400 detects a fault condition which is configured in `OCP_OUTPUT_CTRL Register (A8h)`, the RAA489400 asserts the `OCP#` pin to low. When all fault conditions are removed in `FAULT_STATUS (1Fh)` and `VENDOR_STATUS Register (A0h)`, the RAA489400 deasserts `OCP#` pin.
+
+The `OCP#` function is used for a direct notification signal from the RAA489400 to a system (such as a power management circuit or main system SoC) to notify a fault event.
+
+## 5.6 PROCHOT#
+
+RAA489400 supports the `PROCHOT#` function to notify disconnection of a VBUS source device and/or fast role swap event. If the PROCHOT function is enabled in `PROCHOT_EN Register (AAh)`, the RAA489400 asserts `PROCHOT#` when the RAA489400 detects the following conditions based on the configuration in `PROCHOT_EN Register (AAh)`.
+
+- Disconnection of VBUS source device.
+- FRS signal received.
+
+For example, the `PROCHOT#` function is used for a direct notification signal from the RAA489400 to a system (such as a power management circuit or main system SoC) in the event that a USB-C port loses a power source so that a system starts to reduce a VBUS current drawing.
+
+**Table 4. PROCHOT# Assertion Condition for the Event of Disconnection of VBUS Source Device**
+
+| `PROCHOT_EN` `SNK_DETACH_EN` | `SNK_DETACH` `SNK_OPEN` | `VENDOR_STATUS` `SNK_DETCH_PROCHOT` | `PROCHOT#` signal |
+| --- | --- | --- | --- |
+| 0 | Zero | Set to 1b | Deasserted |
+| 0 | Non-Zero | Set to 1b | Deasserted |
+| 1 | Zero | Set to 1b | Deasserted |
+| 1 | Non-Zero | Set to 1b | Asserted |
+
+<!-- page 30 -->
+
+**Table 5. PROCHOT# Assertion Condition for the Event of FRS Signal Received**
+
+| `PROCHOT_EN` `FRS_EN` | `POWER_CONTROL` Fast Role Swap Enable | `ALERT_EXTERNED` Sink Fast Role Swap | `PROCHOT#` signal |
+| --- | --- | --- | --- |
+| 0 | 0b | Set to 0b | Deasserted |
+| 0 | 1b | Set to 0b | Deasserted |
+| 1 | 0b | Set to 0b | Deasserted |
+| 1 | 1b | Set to 1b | Asserted |
+
+## 5.7 GPIO
+
+The RAA489400 supports the configurable general-purpose input and output with the following functions. The following function can be configured in `GPIO1_CTRL Register (82h)`, `GPIO2_CTRL Register (83h)`, `GPIO3_CTRL Register (84h)`, `GPIO4_CTRL Register (85h)`, `VBUS_PATH_CTRL Register (86h)`, `VBUS_GPIO_CTRL Register (87h)`, and `GPIO_OC_EN Register (89h)`.
+
+1. VBUS source power switch enable function (see Source Path Control).
+2. VBUS sink power switch enable function (see Sink Path Control).
+3. Overcurrent Input (as `STANDARD_INPUT` in TCPCI specification). (See Overcurrent Input.)
+4. General purpose input.
+5. General purpose output (push-pull).
+6. General Purpose output (open-drain).
+
+### 5.7.1 Overcurrent Input
+
+The RAA489400 supports the Overcurrent Input function that is defined in `STANDARD_INPUT_CAPABILITIES Register` as a TCPCi specification to detect a fault condition from an external VBUS power switch.
+
+An input status is shown in `GPIO1_CTRL Register (82h)`, `GPIO2_CTRL Register (83h)`, `GPIO3_CTRL Register (84h)`, and/or `GPIO4_CTRL Register (85h)` as well as `FAULT_STATUS (1Fh)` for the TCPM when a GPIO is enabled as an Overcurrent Input function in `GPIO_OC_EN Register (89h)`.
+
+In addition, if a fault condition is detected from an external VBUS power switch, a GPIO is enabled as an Overcurrent Input function in `GPIO_OC_EN Register (89h)`, and the `OCP#` output is enabled in `OCP_OUTPUT_CTRL Register (A8h)`, the RAA489400 asserts the `OCP#` pin to low.
+
+## 5.8 Clock Management
+
+The RAA489400 supports the integrated oscillators for a 30kHz and 24MHz internal clock. The 30kHz oscillator always works. The 24MHz oscillator can be disabled by the TCPM with the `Stop_24MHz_OSC` bit in `TYPE_C_PRAMETER Register (E2h)` when no USB-C device is connected to the RAA489400. When `CC1`/`CC2` status is changed or I²C access is received, the 24MHz clock is automatically enabled and the `Stop_24MHz_OSC` bit is automatically cleared in `TYPE_C_PRAMETER Register (E2h)`. The `Stop_24MHz_OSC` bit in `TYPE_C_PRAMETER Register (E2h)` reduces power consumption.

REN_RAA489400/06-general-smbus-i2c-architecture.md

@@ -0,0 +1,220 @@
+<!-- page 31 -->
+
+# 6. General SMBus/I²C Architecture
+
+![Figure 14. General SMBus Architecture](06-general-smbus-i2c-architecture/figure-14.png)
+
+## 6.1 Data Validity
+
+The data on the SDA line must be stable during the HIGH period of the SCL unless generating a START or STOP condition. The HIGH or LOW state of the data line can change only when the clock signal on the SCL line is LOW. See Figure 15.
+
+![Figure 15. Data Validity](06-general-smbus-i2c-architecture/figure-15.png)
+
+## 6.2 START and STOP Conditions
+
+Figure 16 shows that the START condition is a HIGH to LOW transition of the SDA line while SCL is HIGH.
+
+The STOP condition is a LOW to HIGH transition on the SDA line while SCL is HIGH. A STOP condition must be sent before each START condition.
+
+<!-- page 32 -->
+
+![Figure 16. Start and Stop Waveforms](06-general-smbus-i2c-architecture/figure-16.png)
+
+## 6.3 Acknowledge (ACK)
+
+Each address and data transmission uses nine clock pulses. The ninth pulse is the Acknowledge bit (ACK). After the start condition, the TCPM sends seven slave target address bits and a R/W bit during the next eight clock pulses. During the ninth clock pulse, the device that recognizes its own address holds the data line LOW to acknowledge (see Figure 17). Both the TCPM and slave target use the ACK bit to acknowledge receipt of register addresses and data.
+
+![Figure 17. Acknowledge on the SMBus](06-general-smbus-i2c-architecture/figure-17.png)
+
+## 6.4 Writing Single Byte Registers
+
+When writing to a single byte register, use the following transaction.
+
+```
+S | Slave Address | Wr(0) | A(0) | Register Address | A(0) | Write Data | A(0) | P
+```
+
+| # | Field | Value |
+| --- | --- | --- |
+| 1 | `S` | START |
+| 2 | Slave Address | 7-bit |
+| 3 | `Wr` | (0) |
+| 4 | `A` | (0) |
+| 5 | Register Address | 8-bit |
+| 6 | `A` | (0) |
+| 7 | Write Data | 8-bit |
+| 8 | `A` | (0) |
+| 9 | `P` | STOP |
+
+![Figure 18. Writing Single Byte Registers](06-general-smbus-i2c-architecture/figure-18.png)
+
+## 6.5 Reading Single Byte Registers
+
+When reading to a single byte register, use the following transaction.
+
+```
+S  | Slave Address | Wr(0) | A(0) | Register Address | A(0) | ...
+Sr | Slave Address | Rd(1) | A(0) | Read Data | N(1) | P
+```
+
+| # | Field | Value |
+| --- | --- | --- |
+| 1 | `S` | START |
+| 2 | Slave Address | 7-bit |
+| 3 | `Wr` | (0) |
+| 4 | `A` | (0) |
+| 5 | Register Address | 8-bit |
+| 6 | `A` | (0) |
+| 7 | `Sr` | Repeated START |
+| 8 | Slave Address | 7-bit |
+| 9 | `Rd` | (1) |
+| 10 | `A` | (0) |
+| 11 | Read Data | 8-bit (shaded = data returned by the target) |
+| 12 | `N` | (1) NACK |
+| 13 | `P` | STOP |
+
+![Figure 19. Reading Single Byte Registers](06-general-smbus-i2c-architecture/figure-19.png)
+
+<!-- page 33 -->
+
+## 6.6 Writing Two-Byte Registers
+
+When writing to a two-byte register, use the following transaction.
+
+```
+S | Slave Address | Wr(0) | A(0) | Register Address | A(0) | Write Data (Low) | A(0) | Write Data (High) | A(0) | P
+```
+
+| # | Field | Value |
+| --- | --- | --- |
+| 1 | `S` | START |
+| 2 | Slave Address | 7-bit |
+| 3 | `Wr` | (0) |
+| 4 | `A` | (0) |
+| 5 | Register Address | 8-bit |
+| 6 | `A` | (0) |
+| 7 | Write Data (Low) | 8-bit |
+| 8 | `A` | (0) |
+| 9 | Write Data (High) | 8-bit |
+| 10 | `A` | (0) |
+| 11 | `P` | STOP |
+
+![Figure 20. Writing Two-Byte Registers](06-general-smbus-i2c-architecture/figure-20.png)
+
+## 6.7 Reading Two-Byte Registers
+
+When reading a two-byte register, use the following transaction.
+
+```
+S  | Slave Address | Wr(0) | A(0) | Register Address | A(0) | ...
+Sr | Slave Address | Rd(1) | A(0) | Read Data (Low) | A(0) | Read Data (High) | N(1) | P
+```
+
+| # | Field | Value |
+| --- | --- | --- |
+| 1 | `S` | START |
+| 2 | Slave Address | 7-bit |
+| 3 | `Wr` | (0) |
+| 4 | `A` | (0) |
+| 5 | Register Address | 8-bit |
+| 6 | `A` | (0) |
+| 7 | `Sr` | Repeated START |
+| 8 | Slave Address | 7-bit |
+| 9 | `Rd` | (1) |
+| 10 | `A` | (0) |
+| 11 | Read Data (Low) | 8-bit (shaded) |
+| 12 | `A` | (0) |
+| 13 | Read Data (High) | 8-bit (shaded) |
+| 14 | `N` | (1) NACK |
+| 15 | `P` | STOP |
+
+![Figure 21. Reading Two-Byte Registers](06-general-smbus-i2c-architecture/figure-21.png)
+
+## 6.8 Writing the TRANSMIT_BUFFER
+
+When writing to the `TRANSMIT_BUFFER` register, use the following transaction.
+
+```
+S | Slave Address | Wr(0) | A(0) | Register Address (TRANSMIT_BUFFER) | A(0) | ...
+  | Write Data (I2C_WRITE_BYTE_COUNT = M + 1) | A(0)
+  | Write Data (TX_BUF_BYTE_0) | A(0) | ...
+  | Write Data (TX_BUF_BYTE_M) | A(0) | P
+```
+
+| # | Field | Value |
+| --- | --- | --- |
+| 1 | `S` | START |
+| 2 | Slave Address | 7-bit |
+| 3 | `Wr` | (0) |
+| 4 | `A` | (0) |
+| 5 | Register Address (`TRANSMIT_BUFFER`) | 8-bit |
+| 6 | `A` | (0) |
+| 7 | Write Data (`I2C_WRITE_BYTE_COUNT` = M + 1) | 8-bit |
+| 8 | `A` | (0) |
+| 9 | Write Data (`TX_BUF_BYTE_0`) | 8-bit |
+| 10 | `A` | (0) |
+| 11 | `・・・` | Additional `TX_BUF_BYTE_n` / `A (0)` pairs |
+| 12 | Write Data (`TX_BUF_BYTE_M`) | 8-bit |
+| 13 | `A` | (0) |
+| 14 | `P` | STOP |
+
+![Figure 22. Writing the TRANSMIT_BUFFER](06-general-smbus-i2c-architecture/figure-22.png)
+
+## 6.9 Reading the RECEIVE_BUFFER
+
+When reading the `RECEIVE_BUFFER` register, use the following transaction.
+
+```
+S  | Slave Address | Wr(0) | A(0) | Register Address (RECEIVE_BUFFER) | A(0) | ...
+Sr | Slave Address | Rd(1) | A(0)
+   | Read Data (READABLE_BYTE_COUNT = M + 2) | A(0)
+   | Read Data (RX_BUF_FRAME_TYPE) | A(0) | ...
+   | Read Data (RX_BUF_BYTE_0) | A(0) | ...
+   | Read Data (RX_BUF_BYTE_M) | N(1) | P
+```
+
+| # | Field | Value |
+| --- | --- | --- |
+| 1 | `S` | START |
+| 2 | Slave Address | 7-bit |
+| 3 | `Wr` | (0) |
+| 4 | `A` | (0) |
+| 5 | Register Address (`RECEIVE_BUFFER`) | 8-bit |
+| 6 | `A` | (0) |
+| 7 | `Sr` | Repeated START |
+| 8 | Slave Address | 7-bit |
+| 9 | `Rd` | (1) |
+| 10 | `A` | (0) |
+| 11 | Read Data (`READABLE_BYTE_COUNT` = M + 2) | 8-bit (shaded) |
+| 12 | `A` | (0) |
+| 13 | Read Data (`RX_BUF_FRAME_TYPE`) | 8-bit (shaded) |
+| 14 | `A` | (0) |
+| 15 | Read Data (`RX_BUF_BYTE_0`) | 8-bit (shaded) |
+| 16 | `A` | (0) |
+| 17 | `・・・` | Additional `RX_BUF_BYTE_n` / `A (0)` pairs |
+| 18 | Read Data (`RX_BUF_BYTE_M`) | 8-bit (shaded) |
+| 19 | `N` | (1) NACK |
+| 20 | `P` | STOP |
+
+![Figure 23. Reading the RECEIVE_BUFFER](06-general-smbus-i2c-architecture/figure-23.png)
+
+## 6.10 Reading the Alert Response Address
+
+When reading the Alert Response Address register, use the following transaction.
+
+```
+S | Alert Response Address (0x0C) | Rd(1) | A(0) | Address | Wr(0) | N(1) | P
+```
+
+| # | Field | Value |
+| --- | --- | --- |
+| 1 | `S` | START |
+| 2 | Alert Response Address | `0x0C` |
+| 3 | `Rd` | (1) |
+| 4 | `A` | (0) |
+| 5 | Address | 7-bit (shaded = returned by the target) |
+| 6 | `Wr` | (0) |
+| 7 | `N` | (1) NACK |
+| 8 | `P` | STOP |
+
+![Figure 24. Reading the Alert Response Address](06-general-smbus-i2c-architecture/figure-24.png)

REN_RAA489400/08-layout.md

@@ -0,0 +1,46 @@
+# RAA489400 Datasheet
+
+<!-- page 79 -->
+
+# 8. Layout
+
+| Pin # | Pin Name | Layout Guidelines |
+| --- | --- | --- |
+| 2 | `CC1` | Route the trace with sufficient width. Place decoupling capacitor to filter the noise. Renesas recommends placing the charger CC pins as close to the USB connector as possible, avoid stubs on the CC lines, and route the CC lines with about the same length. |
+| 26 | `CC2` | Route the trace with sufficient width. Place decoupling capacitor to filter the noise. Renesas recommends placing the charger CC pins as close to the USB connector as possible, avoid stubs on the CC lines, and route the CC lines with about the same length. |
+| 3 | `RD1` | Connect to `CC1`, if dead battery Rd needs to be supported. |
+| 25 | `RD2` | Connect to `CC2`, if dead battery Rd needs to be supported. |
+| 8 | `GPIO1` | Digital pin, open-drain, push-pull output or input. No special consideration. |
+| 7 | `GPIO2` | Digital pin, open-drain, push-pull output or input. No special consideration. |
+| 6 | `GPIO3` | Digital pin, open-drain, push-pull output or input. No special consideration. |
+| 5 | `GPIO4` | Digital pin, open-drain, push-pull output or input. No special consideration. |
+| 9 | `OCP#` | Digital pin, open-drain output. No special consideration. |
+| 20 | `SNK_DISCHG` | Run a dedicated trace from the internal sink power rail to the pin. |
+| 32 | `PROCHOT#` | Digital pin, open-drain output. No special consideration. |
+| 10 | `PROG` | Signal pin. Place the `PROG` programming resistor in the general proximity of the controller. |
+| 29 | `SDA` | Digital pins. No special consideration. Run the `SDA` and `SCL` traces in parallel. |
+| 28 | `SCL` | Digital pins. No special consideration. Run the `SDA` and `SCL` traces in parallel. |
+| 31 | `ALERT#` | Digital pin, open-drain output. No special consideration. |
+| 19 | `VSNK_SRC` | Run this trace with sufficient width in parallel fashion with the `VSNK_GATE` trace. |
+| 18 | `VSNK_GATE` | Run this trace with sufficient width in parallel fashion with the `VSNK_SRC` trace. |
+| 22 | `VSRC_SRC` | Run this trace with sufficient width in parallel fashion with the `VSRC_GATE` trace. |
+| 21 | `VSRC_GATE` | Run this trace with sufficient width in parallel fashion with the `VSRC_SRC` trace. |
+| 23 | `VSRC_BOOT` | Connect to `VSRC_SRC` through a capacitor. |
+| 16 | `CSIN` | Run two dedicated traces with sufficient width in parallel (close to each other to minimize the loop area) from the two terminals of the adapter current-sensing resistor to the IC. Place the Differential mode and common-mode RC filter components in the general proximity of the controller. Route the current-sensing traces through vias to connect the center of the pads or route the traces into the pads from the inside of the current-sensing resistor. The following drawings show the two preferred ways of routing current-sensing traces. |
+| 15 | `CSIP` | Run two dedicated traces with sufficient width in parallel (close to each other to minimize the loop area) from the two terminals of the adapter current-sensing resistor to the IC. Place the Differential mode and common-mode RC filter components in the general proximity of the controller. Route the current-sensing traces through vias to connect the center of the pads or route the traces into the pads from the inside of the current-sensing resistor. The following drawings show the two preferred ways of routing current-sensing traces. |
+| 14 | `VBUS` | Run a dedicated trace from the `VBUS` to the pin. |
+| 12 | `VSYS33` | Run a dedicated trace from the system to the pin. |
+| 30 | `VCONN_POWER` | Place the decoupling capacitor in the general proximity of the controller. Route the trace with sufficient width. |
+| 13 | `VDD33` | Place the decoupling capacitor in the general proximity of the controller. Route the trace with sufficient width. |
+| 4 | `VDD25` | Place the decoupling capacitor in the general proximity of the controller. Route the trace with sufficient width. |
+| 24 | `GND` | Connect this pin to the ground plane. |
+| 1, 7, 17, 23 | `NC` | No connection. Although open, soldering is required. |
+
+![Current-sensing trace routing; printed unnumbered inside the CSIN/CSIP cell of the table above](08-layout/current-sensing-trace-routing.png)
+
+---
+
+R16DS0292EU0100 Rev.1.00
+Aug 27, 2024
+
+Page 79

REN_RAA489400/09-11-package-ordering-revision.md

@@ -0,0 +1,33 @@
+<!-- page 80 -->
+
+# RAA489400 Datasheet
+
+## 9. Package Outline Drawing
+
+The package outline drawing is located at the end of this document and is accessible from the Renesas website. The package information is the most current data available and is subject to change without revision of this document
+
+## 10. Ordering Information
+
+| Part Number<sup>[1][2]</sup> | Part Marking | Package Description<sup>[3]</sup><br>(RoHS Compliant) | Pkg. Dwg # | Carrier Type<sup>[4]</sup> | Temp. Range |
+| --- | --- | --- | --- | --- | --- |
+| RAA489400ARGNP#HA0 | 400AR | 32 Ld 3.0×5.0mm FCQFN | L32.3x5 | Reel, 6k | -10 to +100°C |
+| RAA489400ARGNP#MA0 | 400AR | 32 Ld 3.0×5.0mm FCQFN | L32.3x5 | Reel, 1k | -10 to +100°C |
+| RAA489400A3GNP#HA0 | 400A3 | 32 Ld 3.0×5.0mm FCQFN | L32.3x5 | Reel, 6k | -40 to +105°C |
+| RAA489400A3GNP#MA0 | 400A3 | 32 Ld 3.0×5.0mm FCQFN | L32.3x5 | Reel, 1k | -40 to +105°C |
+
+1. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020.
+2. The Moisture Sensitivity Level (MSL) rating is 3. For more information about MSL, see TB363.
+3. For the PB-Free Profile, see TB493.
+4. See TB347 for details about reel specifications.
+
+## 11. Revision History
+
+| Revision | Date | Description |
+| --- | --- | --- |
+| 1.00 | Aug 27, 2024 | Initial release. |
+
+---
+
+R16DS0292EU0100 Rev.1.00
+Aug 27, 2024
+Page 80

REN_RAA489400/TOC.md

@@ -0,0 +1,151 @@
+# RAA489400 Datasheet — Table of Contents
+
+Markdown transcription of `REN_RAA489400_DST_20240827.pdf` (Renesas RAA489400
+USB Type-C Port Controller), Rev.1.00, Aug 27 2024, document `R16DS0292EU0100`.
+
+The datasheet was split into the per-chapter PDFs in this folder; each has a
+matching `.md` transcription and, where the chapter contains figures, a folder
+of extracted PNGs. Page numbers below are the printed datasheet pages, and are
+mirrored in the transcriptions as `<!-- page N -->` markers.
+
+## Chapters
+
+| # | Chapter | Pages | Source PDF | Figures |
+|---|---|---|---|---|
+| 1 | [Overview](01-overview.md) | 5–10 | [pdf](01-overview.pdf) | 9 |
+| 2 | [Pin Information](02-pin-information.md) | 11–13 | [pdf](02-pin-information.pdf) | 1 |
+| 3 | [Specifications](03-specifications.md) | 14–19 | [pdf](03-specifications.pdf) | — |
+| 4 | [Typical Performance Graphs](04-typical-performance-graphs.md) | 20 | [pdf](04-typical-performance-graphs.pdf) | 2 |
+| 5 | [Functional Description](05-functional-description.md) | 21–30 | [pdf](05-functional-description.pdf) | 1 |
+| 6 | [General SMBus/I²C Architecture](06-general-smbus-i2c-architecture.md) | 31–33 | [pdf](06-general-smbus-i2c-architecture.pdf) | 11 |
+| 7 | [Registers](07-registers.md) | 34–78 | [pdf](07-registers.pdf) | — |
+| 8 | [Layout](08-layout.md) | 79 | [pdf](08-layout.pdf) | 1 |
+| 9–11 | [Package, Ordering, Revision History](09-11-package-ordering-revision.md) | 80 | [pdf](09-11-package-ordering-revision.pdf) | — |
+
+## Sections
+
+- [1. Overview](01-overview.md#1-overview)
+  - [1.1 Block Diagram](01-overview.md#11-block-diagram)
+  - [1.2 Typical Application](01-overview.md#12-typical-application)
+- [2. Pin Information](02-pin-information.md#2-pin-information)
+  - [2.1 Pin Assignments](02-pin-information.md#21-pin-assignments)
+  - [2.2 Pin Descriptions](02-pin-information.md#22-pin-descriptions)
+  - [2.3 Unused Pin Termination](02-pin-information.md#23-unused-pin-termination)
+- [3. Specifications](03-specifications.md#3-specifications)
+  - [3.1 Absolute Maximum Ratings](03-specifications.md#31-absolute-maximum-ratings)
+  - [3.2 Recommended Operating Conditions](03-specifications.md#32-recommended-operating-conditions)
+  - [3.3 Thermal Specifications](03-specifications.md#33-thermal-specifications)
+  - [3.4 Electrical Specifications](03-specifications.md#34-electrical-specifications)
+  - [3.5 SMBus Timing Specification](03-specifications.md#35-smbus-timing-specification)
+- [4. Typical Performance Graphs](04-typical-performance-graphs.md#4-typical-performance-graphs)
+- [5. Functional Description](05-functional-description.md#5-functional-description)
+  - [5.1 Start-Up](05-functional-description.md#51-start-up)
+  - [5.2 Programming Resistors](05-functional-description.md#52-programming-resistors)
+  - [5.3 USB Type-C Port Controller Interface](05-functional-description.md#53-usb-type-c-port-controller-interface)
+    - [5.3.1 USB PD BMC PHY](05-functional-description.md#531-usb-pd-bmc-phy)
+    - [5.3.2 USB Type-C Current Mode](05-functional-description.md#532-usb-type-c-current-mode)
+    - [5.3.3 VCONN Mux](05-functional-description.md#533-vconn-mux)
+    - [5.3.4 Source Path Control](05-functional-description.md#534-source-path-control)
+    - [5.3.5 Sink Path Control](05-functional-description.md#535-sink-path-control)
+    - [5.3.6 Bi-directional VBUS Source and Sink Path Control](05-functional-description.md#536-bi-directional-vbus-source-and-sink-path-control)
+    - [5.3.7 VBUS Monitoring and Measurement](05-functional-description.md#537-vbus-monitoring-and-measurement)
+    - [5.3.8 Internal Sink Path Discharge](05-functional-description.md#538-internal-sink-path-discharge)
+    - [5.3.9 Initial Sink Fast Role Swap](05-functional-description.md#539-initial-sink-fast-role-swap)
+  - [5.4 Protection Features](05-functional-description.md#54-protection-features)
+    - [5.4.1 VBUS Overcurrent Protection](05-functional-description.md#541-vbus-overcurrent-protection)
+    - [5.4.2 VBUS Overvoltage Protection](05-functional-description.md#542-vbus-overvoltage-protection)
+    - [5.4.3 VBUS Source Undervoltage Protection](05-functional-description.md#543-vbus-source-undervoltage-protection)
+    - [5.4.4 VBUS Source Reverse Voltage Protection](05-functional-description.md#544-vbus-source-reverse-voltage-protection)
+    - [5.4.5 VCONN Overcurrent Protection](05-functional-description.md#545-vconn-overcurrent-protection)
+    - [5.4.6 VCONN Overvoltage Protection](05-functional-description.md#546-vconn-overvoltage-protection)
+    - [5.4.7 VCONN Undervoltage Protection](05-functional-description.md#547-vconn-undervoltage-protection)
+    - [5.4.8 VCONN Over-temperature Protection](05-functional-description.md#548-vconn-over-temperature-protection)
+    - [5.4.9 VCONN Reverse Voltage Protection](05-functional-description.md#549-vconn-reverse-voltage-protection)
+  - [5.5 OCP# Output](05-functional-description.md#55-ocp-output)
+  - [5.6 PROCHOT#](05-functional-description.md#56-prochot)
+  - [5.7 GPIO](05-functional-description.md#57-gpio)
+    - [5.7.1 Overcurrent Input](05-functional-description.md#571-overcurrent-input)
+  - [5.8 Clock Management](05-functional-description.md#58-clock-management)
+- [6. General SMBus/I²C Architecture](06-general-smbus-i2c-architecture.md#6-general-smbusi²c-architecture)
+  - [6.1 Data Validity](06-general-smbus-i2c-architecture.md#61-data-validity)
+  - [6.2 START and STOP Conditions](06-general-smbus-i2c-architecture.md#62-start-and-stop-conditions)
+  - [6.3 Acknowledge (ACK)](06-general-smbus-i2c-architecture.md#63-acknowledge-ack)
+  - [6.4 Writing Single Byte Registers](06-general-smbus-i2c-architecture.md#64-writing-single-byte-registers)
+  - [6.5 Reading Single Byte Registers](06-general-smbus-i2c-architecture.md#65-reading-single-byte-registers)
+  - [6.6 Writing Two-Byte Registers](06-general-smbus-i2c-architecture.md#66-writing-two-byte-registers)
+  - [6.7 Reading Two-Byte Registers](06-general-smbus-i2c-architecture.md#67-reading-two-byte-registers)
+  - [6.8 Writing the TRANSMIT_BUFFER](06-general-smbus-i2c-architecture.md#68-writing-the-transmit_buffer)
+  - [6.9 Reading the RECEIVE_BUFFER](06-general-smbus-i2c-architecture.md#69-reading-the-receive_buffer)
+  - [6.10 Reading the Alert Response Address](06-general-smbus-i2c-architecture.md#610-reading-the-alert-response-address)
+- [7. Registers](07-registers.md#7-registers)
+  - [7.1 Register Map](07-registers.md#71-register-map) — full `00h`–`FFh` address map
+  - [7.2 Register Descriptions](07-registers.md#72-register-descriptions) — 63 registers, `VENDOR_ID` (`00h`) through `TYPE_C_PRAMETER` (`E2h`)
+- [8. Layout](08-layout.md#8-layout)
+- [9. Package Outline Drawing](09-11-package-ordering-revision.md#9-package-outline-drawing)
+- [10. Ordering Information](09-11-package-ordering-revision.md#10-ordering-information)
+- [11. Revision History](09-11-package-ordering-revision.md#11-revision-history)
+
+## Figures
+
+| # | Title | Image | In chapter |
+|---|---|---|---|
+| 1 | Block Diagram | [png](01-overview/figure-01.png) | [1.1](01-overview.md#11-block-diagram) |
+| 2 | Typical USB-C Application, TCPC + TCPM, DRP — VBUS SNK up to 48V, SRC up to 5V | [png](01-overview/figure-02.png) | [1.2](01-overview.md#12-typical-application) |
+| 3 | Typical USB-C Application, Source Only — VBUS SRC up to 5V | [png](01-overview/figure-03.png) | [1.2](01-overview.md#12-typical-application) |
+| 4 | Typical USB-C Application, Sink Only — VBUS SNK up to 48V | [png](01-overview/figure-04.png) | [1.2](01-overview.md#12-typical-application) |
+| 5 | Typical USB-C Application, DRP with GPIO Control | [png](01-overview/figure-05.png) | [1.2](01-overview.md#12-typical-application) |
+| 6 | Typical USB-C Application, Source Only with GPIO Control | [png](01-overview/figure-06.png) | [1.2](01-overview.md#12-typical-application) |
+| 7 | Typical USB-C Application, Sink Only with GPIO Control | [png](01-overview/figure-07.png) | [1.2](01-overview.md#12-typical-application) |
+| 8 | USB-C Application, DRP with `VSNK_GATE` + GPIO Control — SNK/SRC up to 48V | [png](01-overview/figure-08.png) | [1.2](01-overview.md#12-typical-application) |
+| 9 | USB-C Application, Bi-directional DRP with GPIO Control — SNK/SRC up to 48V | [png](01-overview/figure-09.png) | [1.2](01-overview.md#12-typical-application) |
+| 10 | Pin Assignments – Top View | [png](02-pin-information/figure-10.png) | [2.1](02-pin-information.md#21-pin-assignments) |
+| 11 | Startup VSYS33 Powered (2.0ms/Div, 2.0V/Div) | [png](04-typical-performance-graphs/figure-11.png) | [4](04-typical-performance-graphs.md#4-typical-performance-graphs) |
+| 12 | Startup from VBUS | [png](04-typical-performance-graphs/figure-12.png) | [4](04-typical-performance-graphs.md#4-typical-performance-graphs) |
+| 13 | Typical Multiport Sink Only | [png](05-functional-description/figure-13.png) | [5.3.6](05-functional-description.md#536-bi-directional-vbus-source-and-sink-path-control) |
+| 14 | General SMBus Architecture | [png](06-general-smbus-i2c-architecture/figure-14.png) | [6](06-general-smbus-i2c-architecture.md#6-general-smbusi²c-architecture) |
+| 15 | Data Validity | [png](06-general-smbus-i2c-architecture/figure-15.png) | [6.1](06-general-smbus-i2c-architecture.md#61-data-validity) |
+| 16 | Start and Stop Waveforms | [png](06-general-smbus-i2c-architecture/figure-16.png) | [6.2](06-general-smbus-i2c-architecture.md#62-start-and-stop-conditions) |
+| 17 | Acknowledge on the SMBus | [png](06-general-smbus-i2c-architecture/figure-17.png) | [6.3](06-general-smbus-i2c-architecture.md#63-acknowledge-ack) |
+| 18 | Writing Single Byte Registers | [png](06-general-smbus-i2c-architecture/figure-18.png) | [6.4](06-general-smbus-i2c-architecture.md#64-writing-single-byte-registers) |
+| 19 | Reading Single Byte Registers | [png](06-general-smbus-i2c-architecture/figure-19.png) | [6.5](06-general-smbus-i2c-architecture.md#65-reading-single-byte-registers) |
+| 20 | Writing Two-Byte Registers | [png](06-general-smbus-i2c-architecture/figure-20.png) | [6.6](06-general-smbus-i2c-architecture.md#66-writing-two-byte-registers) |
+| 21 | Reading Two-Byte Registers | [png](06-general-smbus-i2c-architecture/figure-21.png) | [6.7](06-general-smbus-i2c-architecture.md#67-reading-two-byte-registers) |
+| 22 | Writing the `TRANSMIT_BUFFER` | [png](06-general-smbus-i2c-architecture/figure-22.png) | [6.8](06-general-smbus-i2c-architecture.md#68-writing-the-transmit_buffer) |
+| 23 | Reading the `RECEIVE_BUFFER` | [png](06-general-smbus-i2c-architecture/figure-23.png) | [6.9](06-general-smbus-i2c-architecture.md#69-reading-the-receive_buffer) |
+| 24 | Reading the Alert Response Address | [png](06-general-smbus-i2c-architecture/figure-24.png) | [6.10](06-general-smbus-i2c-architecture.md#610-reading-the-alert-response-address) |
+| — | *(untitled current-sensing trace routing drawing)* | [png](08-layout/current-sensing-trace-routing.png) | [8](08-layout.md#8-layout) |
+
+The last entry is unnumbered and untitled in the source: it is drawn inside the
+`CSIN`/`CSIP` cell of the layout-guidelines table rather than being a captioned
+figure, so it has no figure number or caption to quote.
+
+## Known issues in the source datasheet
+
+These were transcribed verbatim rather than silently corrected:
+
+- **§3.4** — "SRC 5V VBUS Overvoltage Rising Threshold" is printed with unit
+  **mV** but has values 5.8 / 6.3 / 6.6, which only make sense as volts.
+- **§7.1** — Table 7 cites "Table 57" for both `GPIO_OC_EN` (`89h`) and
+  `VBUS_CTRL` (`90h`), and skips Table 59.
+- **§7.2.6** — the `ALERT` bit B9 (Fault) description is cut off mid-sentence
+  in the printed page: "A fault has occurred in".
+- **§7.2.49** — `VBUS_CTRL` bits 10:8 (`N4`) show a reset of `0000b` for a
+  3-bit field.
+- **§7.2.63** — spelled `TYPE_C_PRAMETER` in the section heading but
+  `TYPE_C_PARAMETER` in Table 72. Other typos kept as printed:
+  `TIME_INTERVALif`, `POWER_COTNROL`, `VBUS_PEAK_CURRENTare`,
+  `SNK_TO_SRC_TIMERON`.
+- **§8** — the `NC` row lists pins `1, 7, 17, 23`, but the same table assigns
+  pin 7 to `GPIO2` and pin 23 to `VSRC_BOOT`.
+- **§9** — contains no package outline drawing or dimension table; it only
+  points to the end of the full datasheet and the Renesas website.
+
+## Transcription notes
+
+- GitHub-flavored Markdown has no `rowspan`, so vertically merged cells in the
+  source are repeated on each row.
+- Tables that break across a page in the source are kept split, with their
+  printed "(Cont.)" captions, so the `<!-- page N -->` markers stay in order.
+- Figures were extracted from the vector PDFs by
+  [`tools/extract-figures.py`](../tools/extract-figures.py); run it inside
+  `nix develop`.