markdowned-datasheets/USB_PD_R3.2/TOC.md

USB Power Delivery Specification — Table of Contents

Markdown transcription of USB_PD_R3.2_V1.2_2026_05_20.pdf (Universal Serial Bus Power Delivery Specification, Release 3.2, Version 1.2, May 20 2026).

The specification was split into the per-chapter PDFs in this folder; each has a matching .md transcription and, where the chapter contains figures, a folder of extracted PNGs. Page numbers below are the printed document pages — which in this PDF are identical to the position in the file (no front-matter offset) — and are mirrored in the transcriptions as <!-- page N --> markers.

Chapters

#	Chapter	Pages	Source PDF	Figures
1	Introduction	21–25	pdf	1
2	Glossary and Info	26–36	pdf	—
3	Port Power Requirements	37–47	pdf	4
4	Power Delivery Electrical Requirements	48–84	pdf	25
5	PD Communications Physical Layer	85–111	pdf	25
6	PD Communications Protocol Message Definitions	112–193	pdf	9
7	PD Communications Protocol Message Usage	194–240	pdf	3
8	Vendor Defined Message Usage and Alternate Modes	241–253	pdf	5
9	State Machine Diagrams	254–391	pdf	102
10	Fast Role Swap (FRS)	392–399	pdf	4
A	Revision History	400–404	pdf	—
B	Contributors	405–416	pdf	—

Total: 178 extracted figures across chapters 1–10.

Chapters 6, 7 and 9 are very large (82, 47 and 138 printed pages) and were transcribed and audited in ~8-page chunks that were concatenated afterwards; the section tree below is capped at 2–3 levels of numbering for these three chapters so the TOC stays usable — the files themselves go deeper (chapter 9 nests to 9.2.26.4.3 and beyond for individual state diagrams).

## Sections

• Chapter 1. Introduction

  • 1.1. Cable and Connectors
  • 1.2. Operational Overview
  • 1.3. USB PD Roles
    • 1.3.1. Source Port
    • 1.3.2. Sink Port
    • 1.3.3. Downstream Facing Port (DFP)
    • 1.3.4. Upstream Facing Port (UFP)
    • 1.3.5. Dual-Role Power (DRP) Ports
    • 1.3.6. Dual-Role Data (DRD) Ports
    • 1.3.7. VCONN Source
    • 1.3.8. Cable Plugs
  • 1.4. Power Delivery Operational Contracts
  • 1.5. Source and Sink Operation in USB PD
    • 1.5.1. General Source-to-Sink Initial Interaction
  • 1.6. Common PD Device Types
  • 1.7. USB-PD Architectural Overview

• Chapter 2. Glossary and Info

  • 2.1. Conventions
    • 2.1.1. Precedence
    • 2.1.2. Keywords
    • 2.1.3. Numbering
  • 2.2. Related Documents
  • 2.3. Terms and Abbreviations

• Chapter 3. Port Power Requirements

  • 3.1. Introduction
  • 3.2. Source Port Power Requirements
    • 3.2.1. General Source Port Requirements
    • 3.2.2. Guaranteed Capability Port
    • 3.2.3. Managed Capability Port
    • 3.2.4. Source Voltage and Current Requirements
    • 3.2.5. Optional Source Voltage/Currents
  • 3.3. Dynamic Power Supply (DPS)
  • 3.4. Sink Power Requirements
    • 3.4.1. Sink Power Rule Considerations
    • 3.4.2. Sink Requirements
  • 3.5. Sink with Acessory Support
  • 3.6. PDUSB Device Requirements

• Chapter 4. Power Delivery Electrical Requirements

  • 4.1. Source Requirements
    • 4.1.1. Behavioral Aspects
    • 4.1.2. Source Bulk Capacitance
    • 4.1.3. Source Transitions
    • 4.1.4. Non-application of VBUS Slew Rate Limits
    • 4.1.5. Robust Source Operation
    • 4.1.6. Source Peak Current Operation
    • 4.1.7. Source Capabilities Extended Parameters
  • 4.2. Sink Requirements
    • 4.2.1. Behavioral Aspects
    • 4.2.2. Sink Bulk Capacitance
    • 4.2.3. Sink Standby
    • 4.2.4. Suspend Power Consumption
    • 4.2.5. Zero Negotiated Power
    • 4.2.6. Transient Load Behavior
    • 4.2.7. Considerations for Current Limit in PPS Mode
    • 4.2.8. Sink Peak Current Operation
    • 4.2.9. Robust Sink Operation
  • 4.3. Dual Role Ports
    • 4.3.1. Swap Standby for the Initial Source
    • 4.3.2. Swap Standby for the Initial Sink
    • 4.3.3. Power Role Swap Sequence
  • 4.4. Response to Hard Resets
    • 4.4.1. Hard Reset Sequence
  • 4.5. Transitions
    • 4.5.1. Fixed and AVS transitions
    • 4.5.2. PPS voltage or current changes
  • 4.6. VCONN Power Cycle
  • 4.7. Electrical Parameters
    • 4.7.1. Source Electrical Parameters
    • 4.7.2. Sink Electrical Parameters
    • 4.7.3. Common Electrical Parameters

• Chapter 5. PD Communications Physical Layer

  • 5.1. Overview
  • 5.2. Signaling Through DC Biasing
    • 5.2.1. Power Role Indication
    • 5.2.2. Collision Avoidance
  • 5.3. BMC Signaling
    • 5.3.1. Transmission
    • 5.3.2. Reception
    • 5.3.3. Electrical Characteristics for Transmission and Reception
    • 5.3.4. Encoding and Signaling
  • 5.4. Built in Self-Test (BIST)
    • 5.4.1. BIST Carrier Mode
  • 5.5. PD Communications Physical Layer Parameters
    • 5.5.1. BMC Common Parameters
    • 5.5.2. BMC Transmitter Parameters
    • 5.5.3. BMC Receiver Parameters

• Chapter 6. PD Communications Protocol Message Definitions

  • 6.1. Overview
  • 6.2. Message Construction
  • 6.3. Control Message
  • 6.4. Data Message
  • 6.5. Extended Message
  • 6.6. Value Parameters

• Chapter 7. PD Communications Protocol Message Usage

  • 7.1. Reset
  • 7.2. Collision Avoidance
  • 7.3. Message Discarding
  • 7.4. Common Messages
  • 7.5. Applicability Tables
  • 7.6. AMS Usages
  • 7.7. Soft Reset AMS
  • 7.8. Data Reset AMS
  • 7.9. Power Negotiation (SPR) AMS
  • 7.10. Power Role Swap AMS
  • 7.11. Fast Role Swap AMS
  • 7.12. Data Role Swap AMS
  • 7.13. VCONN Swap AMS
  • 7.14. Alert AMS Message
  • 7.15. Get Status AMS
  • 7.16. Get PPS Status AMS
  • 7.17. Get Source Capabilities (SPR) AMS
  • 7.18. Get Sink Capabilities (SPR) AMS
  • 7.19. Extended Capabilities AMS
  • 7.20. Battery Capabilities AMS
  • 7.21. Battery Status AMS
  • 7.22. Manufacturer Information AMS
  • 7.23. Country Codes AMS
  • 7.24. Country Information AMS
  • 7.25. Revision Information AMS
  • 7.26. Source Information AMS
  • 7.27. Security AMS
  • 7.28. Firmware Update AMS
  • 7.29. Enter USB AMS
  • 7.30. EPR Mode AMS
  • 7.31. Timers
  • 7.32. Counters

• Chapter 8. Vendor Defined Message Usage and Alternate Modes

  • 8.1. Overview
  • 8.2. Alternate Modes
  • 8.3. General VDM Rules
  • 8.4. Unstructured VDM Rules
  • 8.5. Structured VDM Rules
    • 8.5.1. Structured VDM Version
    • 8.5.2. Object Position
    • 8.5.3. SVID
  • 8.6. Command Usage
    • 8.6.1. Discover Identity
    • 8.6.2. Discover SVIDs
    • 8.6.3. Discover Modes
    • 8.6.4. Enter Mode Command
    • 8.6.5. Exit Mode Command
    • 8.6.6. Attention
  • 8.7. Command Processes
    • 8.7.1. Discovery Process
    • 8.7.2. Entering Alternate Modes
    • 8.7.3. Exiting Alternate Modes

• Chapter 9. State Machine Diagrams

  • 9.1. Protocol Layer State Diagrams
    • 9.1.1. Introduction to Protocol Layer State Diagrams
    • 9.1.2. State Operation
  • 9.2. Policy Engine Layer State Diagrams
    • 9.2.1. Introduction to State diagrams
    • 9.2.2. SenderResponseTimer State Diagram
    • 9.2.3. Policy Engine Source Port State Diagram
    • 9.2.4. Policy Engine Sink Port State Diagram
    • 9.2.5. SOP Soft Reset and Protocol Error State Diagrams
    • 9.2.6. Data Reset State Diagrams
    • 9.2.7. Not Supported Message State Diagrams
    • 9.2.8. Alert State Diagrams
    • 9.2.9. Source/Sink Capabilities Extended State Diagrams
    • 9.2.10. Source Information State Diagrams
    • 9.2.11. Status State Diagrams
    • 9.2.12. Battery Capabilities State Diagrams
    • 9.2.13. Battery Status State Diagrams
    • 9.2.14. Manufacturer Information State Diagrams
    • 9.2.15. Country Codes and Information State Diagrams
    • 9.2.16. Revision State Diagrams
    • 9.2.17. Enter_USB Message State Diagrams
    • 9.2.18. Security State Diagrams
    • 9.2.19. Firmware Update State Diagrams
    • 9.2.20. Dual-Role Port State Diagrams
    • 9.2.21. VCONN Swap State Diagram
    • 9.2.22. Initiator Structured VDM State Diagrams
    • 9.2.23. Responder Structured VDM State Diagrams
    • 9.2.24. DFP Structured VDM State Diagrams
    • 9.2.25. UFP Structured VDM State Diagrams
    • 9.2.26. Cable Plug Specific State Diagrams

• Chapter 10. Fast Role Swap (FRS)

  • 10.1. Introduction
  • 10.2. FRS Initialization
  • 10.3. FRS Sequence
  • 10.4. Initial Source/New Sink
    • 10.4.1. Initial Sink/New Source
    • 10.4.2. Constraints During FRS
  • 10.5. FRS Parameters

• Appendix A. Revision History

• Appendix B. Contributors

  • ACON, Advanced-Connectek, Inc.
  • ASMedia Technology Inc.
  • Advanced Micro Devices
  • Allion Labs, Inc.
  • Analogix Semiconductor, Inc.
  • Apple Inc.
  • Bizlink Technology Inc.
  • Bizlink Technology, Inc.
  • Broadcom Corp.
  • Cadence Design Systems, Inc.
  • Canova Tech
  • Canyon Semiconductor
  • Chrontel, Inc.
  • Cypress Semiconductor
  • Dell Inc.
  • Derun Semiconductor
  • Dialog Semiconductor (UK) Ltd
  • Diodes Incorporated
  • DisplayLink (UK) Ltd.
  • Ellisys
  • Etron Technology, Inc.
  • Fairchild Semiconductor
  • Feature Integration Technology Inc.
  • Foxconn / Hon Hai
  • Fresco Logic Inc.
  • Google Inc.
  • Granite River Labs
  • GuangDong OPPO Mobile Telecommunications Corp., Ltd.
  • HP Inc.
  • Hosiden Corporation
  • Huawei Technologies Co., Ltd.
  • Hynetek Semiconductor Co., Ltd
  • ITE Tech. Inc.
  • Indie Semiconductor
  • Infineon Technologies
  • Intel Corporation
  • Intersil Corporation
  • Japan Aviation Electronics Industry Ltd. (JAE)
  • Keysight Technologies Inc.
  • Kinetic Technologies Inc.
  • LG Electronics Ltd.
  • LG electronics
  • LSI Corporation
  • Lattice Semiconductor Corp
  • LeCroy Corporation
  • Leadtrend
  • Lenovo
  • Lion Semiconductor
  • Luxshare-ICT
  • MCCI Corporation
  • MQP Electronics Ltd.
  • Maxim Integrated Products
  • MediaTek Inc.
  • MegaChips Corporation
  • Microchip Technology Inc.
  • Microsoft Corporation
  • Molex LLC
  • Monolithic Power Systems Inc.
  • Motorola Mobility Inc.
  • NEC Corporation
  • NXP Semiconductors
  • Nexperia B.V.
  • Nokia Corporation
  • ON Semiconductor
  • Obsidian Technology
  • Parade Technologies Inc.
  • Power Forest Technology Corporation
  • Power Integrations
  • Qualcomm, Inc
  • ROHM Co., Ltd.
  • Realtek Semiconductor Corp.
  • Renesas Electronics Corp.
  • Richtek Technology Corporation
  • Ricoh Company Ltd.
  • Rohm Co. Ltd.
  • SMSC
  • ST-Ericsson
  • STMicroelectronics
  • Salcomp Plc
  • Samsung Electronics Co. Ltd.
  • Scosche Industries
  • Seagate Technology LLC
  • Semtech Corporation
  • Siemens Industry Software Inc.
  • Silergy Corp.
  • SiliConch Systems Private Limited
  • Silicon Laboratories, Inc.
  • Sony Group Corporation
  • Specwerkz
  • StarTech.com Ltd.
  • Synopsys, Inc.
  • Tektronix
  • Teledyne-LeCroy
  • Texas Instruments
  • The Silanna Group Pty. Ltd.
  • Total Phase
  • UL LLC
  • Unigraf OY
  • VIA Technologies, Inc.
  • Ventev Mobile
  • Weltrend Semiconductor
  • Western Digital Technologies, Inc.
  • Wilder Technologies
  • Xiaomi Communications Co., Ltd.
  • Zhuhai Ismartware Technology Co., Ltd.
  • eEver Technology, Inc.
  • iST - Integrated Service Technology Inc.
  • Key Contributors to the Revision 3.2 Version 1.2 Specification Rewrite

Figure index

178 figures total. Extracted with tools/extract-figures.py --caption-position above (this spec places the caption ABOVE each figure, unlike the Renesas template the tool was originally written for — see tool notes below). Figure 7.3 has no detectable ink band because an explanatory sentence sits directly under its caption before the diagram starts; it was cropped with an explicit --region.

#	Title	Image	In section
1.1	USB PD Capable Device High Level Architecture	png	1.7. USB-PD Architectural Overview
3.1	SPR Required Source Power Rule Illustration for Fixed PDOs	png	3.2.4. Source Voltage and Current Requirements
3.2	EPR Source Power Rule Illustration for Fixed PDOs	png	3.2.5.3. Extended Power Range (EPR)
3.3	Valid EPR AVS Operating Region	png	3.2.5.3. Extended Power Range (EPR)
3.4	Example of a DPS temperature profile	png	3.3. Dynamic Power Supply (DPS)
4.1	Placement of Source Bulk Capacitance	png	4.1.2. Source Bulk Capacitance
4.2	Application of vNew and vValid limits after tSrcReady or tSrcTransSmall or tSrcTransLarge	png	4.1.2.1.1. Voltage Regulation
4.3	Transition Envelope for Positive Voltage Transitions	png	4.1.3.1. Fixed Voltage Transitions
4.4	Transition Envelope for Negative Voltage Transitions	png	4.1.3.1. Fixed Voltage Transitions
4.5	PPS/AVS Voltage Transitions	png	4.1.3.2.1. Voltage Transitions
4.6	PPS Programmable Voltage and Current Limit	png	4.1.3.2.2. PPS Operation in Current Limit (CL) Mode
4.7	PPS Constant Power	png	4.1.3.2.3. PPS Operation in Constant Power
4.8	Expected PPS Ripple Relative to an LSB	png	4.1.3.2.5. Source AVS/PPS Ripple
4.9	Allowed DNL Errors and Tolerance of Voltage and Current in AVS/PPS Mode	png	4.1.3.2.6. Source DNL Tolerance
4.10	Source Peak Current Overload	png	4.1.6. Source Peak Current Operation
4.11	Holdup Time Measurement	png	4.1.7.3. Holdup Time Field
4.12	Placement of Sink Bulk Capacitance	png	4.2.2. Sink Bulk Capacitance
4.13	Transition Diagram for a Power Role Swap	png	4.3.3. Power Role Swap Sequence
4.14	Source VBUS and VCONN Response to Hard Reset	png	4.4. Response to Hard Resets
4.15	Transition diagram for a Hard Reset	png	4.4.1. Hard Reset Sequence
4.16	Transition Diagram for Large-step voltage increase (Fixed or AVS > vSmallStep)	png	4.5.1.1. Large-step voltage increases (Fixed or AVS)
4.17	Transition Diagram for Small-step voltage increase (AVS ≤ vSmallStep), current unchanged or increased	png	4.5.1.2. Small-step voltage increases (AVS)
4.18	Transition Diagram for Small-step voltage increase (AVS ≤ vSmallStep), current decreased	png	4.5.1.2. Small-step voltage increases (AVS)
4.19	Transition Diagram for voltage unchanged or decreased with current unchanged or increased	png	4.5.1.3. Unchanged or decreased voltage transitions (current unchanged, increased, or decreased)
4.20	Transition Diagram for voltage unchanged or decreased with current decreased	png	4.5.1.3. Unchanged or decreased voltage transitions (current unchanged, increased, or decreased)
4.21	Transition Diagram for PPS voltage increase (CV Mode)	png	4.5.2.1. PPS voltage transitions (CV Mode)
4.22	Transition Diagram for PPS voltage decrease (CV Mode)	png	4.5.2.1. PPS voltage transitions (CV Mode)
4.23	Transition Diagram for PPS current increase (CL Mode)	png	4.5.2.2. PPS current transitions (CL Mode)
4.24	Transition Diagram for PPS current decrease (CL Mode)	png	4.5.2.2. PPS current transitions (CL Mode)
4.25	Data Reset VCONN Power Cycle	png	4.6. VCONN Power Cycle
5.1	Transmit Packet Format	png	5.3.1.1. Packet Formation
5.2	Line Format for Hard Reset and Cable	png	5.3.1.2. Resets
5.3	Receive Packet Interpretation.	png	5.3.2. Reception
5.4	BMC Example	png	5.3.3. Electrical Characteristics for Transmission and Reception
5.5	BMC Transmitter Block Diagram	png	5.3.4. Encoding and Signaling
5.6	BMC Receiver Block Diagram	png	5.3.4. Encoding and Signaling
5.7	BMC Encoded Start of Preamble	png	5.3.4. Encoding and Signaling
5.8	Transmitting or Receiving BMC Encoded Frame Terminated by Zero with High-to-Low Last Transition	png	5.3.4. Encoding and Signaling
5.9	Transmitting or Receiving BMC Encoded Frame Terminated by One with High-to-Low Last Transition	png	5.3.4. Encoding and Signaling
5.10	Transmitting or Receiving BMC Encoded Frame Terminated by Zero with Low-to-High Last Transition	png	5.3.4. Encoding and Signaling
5.11	Transmitting or Receiving BMC Encoded Frame Terminated by One with High-to-Low Last Transition	png	5.3.4. Encoding and Signaling
5.12	BMC Tx 'ONE' Mask.	png	5.3.4.1. Transmit Mask
5.13	BMC Tx 'ZERO' Mask.	png	5.3.4.1. Transmit Mask
5.14	BMC Rx 'ONE' Mask when Sourcing Power	png	5.3.4.2. Receive Masks
5.15	BMC Rx 'ZERO' Mask when Sourcing Power	png	5.3.4.2. Receive Masks
5.16	BMC Rx 'ONE' Mask when Sinking Power	png	5.3.4.2. Receive Masks
5.17	BMC Rx 'ZERO' Mask when Sinking Power	png	5.3.4.2. Receive Masks
5.18	BMC Rx 'ONE' Mask when Power Neutral	png	5.3.4.2. Receive Masks
5.19	BMC Rx 'ZERO' Mask when Power Neutral	png	5.3.4.2. Receive Masks
5.20	Transmitter Load Model for BMC Tx from a Source	png	5.3.4.3. Transmit Load Model
5.21	Transmitter Load Model for BMC Tx from a Sink	png	5.3.4.3. Transmit Load Model
5.22	Example Multi-Drop Configuration showing two DRPs and two Cable Transceivers	png	5.3.4.4. Cable Plug Transceivers.
5.23	Example Multi-Drop Configuration showing a DFP and UFP with a VCONN Source	png	5.3.4.5. Transceiver with VCONN Source Capability
5.24	Transmitter diagram illustrating zDriver	png	5.3.4.7. Source Output Impedance
5.25	Inter-Frame Gap Timings	png	5.3.4.9. Inter-Frame Gap
6.1	Construction of Chunked Extended and Chunk Request Messages	png	6.1.4. Chunking
6.2	Format of PD Packets for Different Message Types	png	6.2. Message Construction
6.3	Figure: EPR_Request Message	png	6.4.8. EPR_Request Message
6.4	Figure: Vendor Defined Message	png	6.4.12. Vendor Defined Message
6.5	Discover Identity Response Format	png	6.4.12.3. Discover Identity
6.6	Discover SVIDs Response Format	png	6.4.12.4. Discover SVIDs
6.7	Example Discover Modes response for a given SVID with 3 Modes	png	6.4.12.5. Discover Mode
6.8	Source Capabilities Message Format	png	6.5.18. EPR_Source_Capabilities Message
6.9	Source Capabilities Message Format (with no EPR PDOs)	png	6.5.18. EPR_Source_Capabilities Message
7.1	Sequence diagram of messaging core between protocol layers	png	7.6.1. Basic Message Exchange
7.2	Basic Message flow indicating possible errors	png	7.6.2. Possible Points of Failure for Message Delivery
7.3	Illustration of process to enter EPR Mode.	png	7.30.1. Process to Enter EPR Mode AMS
8.1	Successful Enter Mode sequence	png	8.6.4. Enter Mode Command
8.2	Unsuccessful Enter Mode sequence due to NAK	png	8.6.4. Enter Mode Command
8.3	Exit Mode sequence	png	8.6.5. Exit Mode Command
8.4	Attention Command Request/response sequence	png	8.6.6. Attention
8.5	Enter/Exit Mode Process	png	8.7.3. Exiting Alternate Modes
9.1	Outline of States	png	9.1.1. Introduction to Protocol Layer State Diagrams
9.2	References to States	png	9.1.1. Introduction to Protocol Layer State Diagrams
9.3	Chunking architecture Showing Message and Control Flow	png	9.1.2.1.1. Architecture of Device Including Chunking Layer
9.4	Chunked Rx State Diagram	png	9.1.2.1.2. Chunked Rx State Diagram
9.5	Chunked Tx State Diagram	png	9.1.2.1.3. Chunked Tx State Diagram
9.6	Chunked Message Router State Diagram	png	9.1.2.1.4. Chunked Message Router State Diagram
9.7	Common Protocol Layer Message Transmission State Diagram	png	9.1.2.2.1. Common Protocol Layer Message Transmission State Diagram
9.8	Source Protocol Layer Message Transmission State Diagram	png	9.1.2.2.2. Source Protocol Layer Message Transmission State Diagram
9.9	Sink Protocol Layer Message Transmission State Diagram	png	9.1.2.2.3. Sink Protocol Layer Message Transmission State Diagram
9.10	Protocol Layer Message reception	png	9.1.2.3. Protocol Layer Message Reception
9.11	Hard/Cable Reset	png	9.1.2.4. Hard Reset operation
9.12	Outline of States	png	9.2.1. Introduction to State diagrams
9.13	References to states	png	9.2.1. Introduction to State diagrams
9.14	Example of State reference with conditions	png	9.2.1. Introduction to State diagrams
9.15	Example of State reference with the same entry and exit	png	9.2.1. Introduction to State diagrams
9.16	SenderResponseTimer Policy Engine State Diagram	png	9.2.2. SenderResponseTimer State Diagram
9.17	Source Port State Diagram	png	9.2.3. Policy Engine Source Port State Diagram
9.18	Sink Port State Diagram	png	9.2.4. Policy Engine Sink Port State Diagram
9.19	SOP Source Port Soft Reset and Protocol Error State Diagram	png	9.2.5.1. SOP Source Port Soft Reset and Protocol Error State Diagram
9.20	Sink Port Soft Reset and Protocol Error Diagram	png	9.2.5.2. SOP Sink Port Soft Reset and Protocol Error State Diagram
9.21	DFP Data_Reset Message State Diagram	png	9.2.6.1. DFP Data_Reset Message State Diagrams
9.22	UFP Data_Reset Message State Diagram	png	9.2.6.2. UFP Data_Reset Message State Diagrams
9.23	Source Port Not Supported Message State Diagram	png	9.2.7.1. Source Port Not Supported Message State Diagram
9.24	Sink Port Not Supported Message State Diagram	png	9.2.7.2. Sink Port Not Supported Message State Diagram
9.25	Source Port Source Alert State Diagram	png	9.2.8.1. Source Port Source Alert State Diagram
9.26	Sink Port Source Alert State Diagram	png	9.2.8.2. Sink Port Source Alert State Diagram
9.27	Sink Port Sink Alert State Diagram	png	9.2.8.3. Sink Port Sink Alert State Diagram
9.28	Source Port Sink Alert State Diagram	png	9.2.8.4. Source Port Sink Alert State Diagram
9.29	Sink Port Get Source Capabilities Extended State Diagram	png	9.2.9.1. Sink Port Get Source Capabilities Extended State Diagram
9.30	Source Give Source Capabilities Extended State Diagram	png	9.2.9.2. Source Give Source Capabilities Extended State Diagram
9.31	Source Port Get Sink Capabilities Extended State Diagram	png	9.2.9.3. Source Port Get Sink Capabilities Extended State Diagram
9.32	Sink Give Sink Capabilities Extended State Diagram	png	9.2.9.4. Sink Give Sink Capabilities Extended State Diagram
9.33	Sink Port Get Source Information State Diagram	png	9.2.10.1. Sink Port Get Source Information State Diagram
9.34	Source Give Source Information State Diagram	png	9.2.10.2. Source Give Source Information State Diagram
9.35	Get Status State Diagram	png	9.2.11.1. Get Status State Diagram
9.36	Give Status State Diagram	png	9.2.11.2. Give Status State Diagram
9.37	Sink Port Get Source PPS Status State Diagram	png	9.2.11.3. Sink Port Get Source PPS Status State Diagram
9.38	Source Give Source PPS Status State Diagram	png	9.2.11.4. Source Give Source PPS Status State Diagram
9.39	Get Battery Capabilities State Diagram	png	9.2.12.1. Get Battery Capabilities State Diagram
9.40	Give Battery Capabilities State Diagram	png	9.2.12.2. Give Battery Capabilities State Diagram
9.41	Get Battery Status State Diagram	png	9.2.13.1. Get Battery Status State Diagram
9.42	Give Battery Status State Diagram	png	9.2.13.2. Give Battery Status State Diagram
9.43	Get Manufacturer Information State Diagram	png	9.2.14.1. Get Manufacturer Information State Diagram
9.44	Give Manufacturer Information State Diagram	png	9.2.14.2. Give Manufacturer Information State Diagram
9.45	Get Country Codes State Diagram	png	9.2.15.1. Get Country Codes State Diagram
9.46	Give Country Codes State Diagram	png	9.2.15.2. Give Country Codes State Diagram
9.47	Get Country Information State Diagram	png	9.2.15.3. Get Country Information State Diagram
9.48	Give Country Information State Diagram	png	9.2.15.4. Give Country Information State Diagram
9.49	Get Revision State Diagram	png	9.2.16.1. Get Revision State Diagram
9.50	Give Revision State Diagram	png	9.2.16.2. Give Revision State Diagram
9.51	DFP Enter_USB Message State Diagram	png	9.2.17.1. DFP Enter_USB Message State Diagrams
9.52	UFP Enter_USB Message State Diagram	png	9.2.17.2. UFP or Cable Plug Enter_USB Message State Diagrams
9.53	Send security Request State Diagram	png	9.2.18.1. Send Security Request State Diagram
9.54	Send security response State Diagram	png	9.2.18.2. Send Security Response State Diagram
9.55	Security response received State Diagram	png	9.2.18.3. Security Response Received State Diagram
9.56	Send firmware update Request State Diagram	png	9.2.19.1. Send Firmware Update Request State Diagram
9.57	Send firmware update response State Diagram	png	9.2.19.2. Send Firmware Update Response State Diagram
9.58	Firmware update response received State Diagram	png	9.2.19.3. Firmware Update Response Received State Diagram
9.59	DFP to UFP Data Role Swap State Diagram	png	9.2.20.1. DFP to UFP Data Role Swap State Diagram
9.60	UFP to DFP Data Role Swap State Diagram	png	9.2.20.2. UFP to DFP Data Role Swap State Diagram
9.61	Dual-Role Port in Source to Sink Power Role Swap State Diagram	png	9.2.20.3. Policy Engine in Source to Sink Power Role Swap State Diagram
9.62	Dual-role Port in Sink to Source Power Role Swap State Diagram	png	9.2.20.4. Policy Engine in Sink to Source Power Role Swap State Diagram
9.63	Dual-Role Port in Source to Sink Power Role Swap State Diagram	png	9.2.20.5. Policy Engine in Source to Sink Fast Role Swap State Diagram
9.64	Dual-role Port in Sink to Source Fast Role Swap State Diagram	png	9.2.20.6. Policy Engine in Sink to Source Fast Role Swap State Diagram
9.65	Dual-Role (Source) Get Source Capabilities diagram	png	9.2.20.7. Dual-Role (Source Port) Get Source Capabilities State Diagram
9.66	Dual-Role (Source) Give Sink Capabilities diagram	png	9.2.20.8. Dual-Role (Source Port) Give Sink Capabilities State Diagram
9.67	Dual-Role (Sink) Get Sink Capabilities State Diagram	png	9.2.20.9. Dual-Role (Sink Port) Get Sink Capabilities State Diagram
9.68	Dual-Role (Sink) Give Source Capabilities State Diagram	png	9.2.20.10. Dual-Role (Sink Port) Give Source Capabilities State Diagram
9.69	Dual-Role (Source) Get Source Capabilities Extended State Diagram	png	9.2.20.11. Dual-Role (Source Port) Get Source Capabilities Extended State Diagram
9.70	Dual-Role (Sink) Give Source Capabilities Extended diagram	png	9.2.20.12. Dual-Role (Sink Port) Give Source Capabilities Extended State Diagram
9.71	Dual-Role (Sink) Get Sink Capabilities Extended State Diagram	png	9.2.20.13. Dual-Role (Sink Port) Get Sink Capabilities Extended State Diagram
9.72	Dual-Role (Source) Give Sink Capabilities Extended diagram	png	9.2.20.14. Dual-Role (Source Port) Give Sink Capabilities Extended State Diagram
9.73	Dual-Role (Source) Get Source Information State Diagram	png	9.2.20.15. Dual-Role (Source Port) Get Source Information State Diagram
9.74	Dual-Role (Source) Give Source Information diagram	png	9.2.20.16. Dual-Role (Sink Port) Give Source Information State Diagram
9.75	VCONN Swap State Diagram	png	9.2.21. VCONN Swap State Diagram
9.76	Initiator to Port VDM Discover Identity State Diagram	png	9.2.22.1. Initiator Structured VDM Discover Identity State Diagram
9.77	Initiator VDM Discover SVIDs State Diagram	png	9.2.22.2. Initiator Structured VDM Discover SVIDs State Diagram
9.78	Initiator VDM Discover Modes State Diagram	png	9.2.22.3. Initiator Structured VDM Discover Modes State Diagram
9.79	Initiator VDM Attention State Diagram	png	9.2.22.4. Initiator Structured VDM Attention State Diagram
9.80	Responder Structured VDM Discover Identity State Diagram	png	9.2.23.1. Responder Structured VDM Discover Identity State Diagram
9.81	Responder Structured VDM Discover SVIDs State Diagram	png	9.2.23.2. Responder Structured VDM Discover SVIDs State Diagram
9.82	Responder Structured VDM Discover Modes State Diagram	png	9.2.23.3. Responder Structured VDM Discover Modes State Diagram
9.83	Receiving a Structured VDM Attention State Diagram	png	9.2.23.4. Receiving a Structured VDM Attention State Diagram
9.84	DFP VDM Mode Entry State Diagram	png	9.2.24.1. DFP Structured VDM Mode Entry State Diagram
9.85	DFP VDM Mode Exit State Diagram	png	9.2.24.2. DFP Structured VDM Mode Exit State Diagram
9.86	UFP Structured VDM Enter Mode State Diagram	png	9.2.25.1. UFP Structured VDM Enter Mode State Diagram
9.87	UFP Structured VDM Exit Mode State Diagram	png	9.2.25.2. UFP Structured VDM Exit Mode State Diagram
9.88	Cable Ready State Diagram	png	9.2.26.1. Cable Plug Cable Ready State Diagram
9.89	Cable Plug Soft Reset State Diagram	png	9.2.26.2.1. Cable Plug Soft Reset State Diagram
9.90	Cable Plug Hard Reset State Diagram	png	9.2.26.2.2. Cable Plug Hard Reset State Diagram
9.91	DFP/VCONN Source Soft Reset or Cable Reset of a Cable Plug or VPD State Diagram	png	9.2.26.2.3. DFP/VCONN Source SOP'/SOP" Soft Reset or Cable Reset of a Cable Plug or VPD State Diagram
9.92	UFP/VCONN Source Soft Reset of a Cable Plug or VPD State Diagram	png	9.2.26.2.4. UFP/VCONN Source SOP'/SOP'' Soft Reset of a Cable Plug or VPD State Diagram
9.93	Source Startup Structured VDM Discover Identity State Diagram	png	9.2.26.2.5. Source Startup Structured VDM Discover Identity of a Cable Plug State Diagram
9.94	Cable Plug Structured VDM Enter Mode State Diagram	png	9.2.26.2.6.1. Cable Plug Structured VDM Enter Mode State Diagram
9.95	Cable Plug Structured VDM Exit Mode State Diagram	png	9.2.26.2.6.2. Cable Plug Structured VDM Exit Mode State Diagram
9.96	Source EPR Mode Entry State Diagram	png	9.2.26.3.1. Source EPR Mode Entry State Diagram
9.97	Sink EPR Mode Entry State Diagram	png	9.2.26.3.1. Source EPR Mode Entry State Diagram
9.98	Source EPR Mode Exit State Diagram	png	9.2.26.3.1. Source EPR Mode Entry State Diagram
9.99	Sink EPR Mode Exit State Diagram	png	9.2.26.3.1. Source EPR Mode Entry State Diagram
9.100	BIST Carrier Mode State Diagram	png	9.2.26.3.1. Source EPR Mode Entry State Diagram
9.101	BIST Test Data Mode State Diagram	png	9.2.26.3.1. Source EPR Mode Entry State Diagram
9.102	BIST Shared Capacity Test Mode State Diagram	png	9.2.26.4.3. BIST Shared Capacity Test Mode State Diagram
10.1	Power Flow Before and After an FRS	png	10.1. Introduction
10.2	FRS Signaling and Receiving Activity Diagrams	png	10.3. FRS Sequence
10.3	FRS Sequence with VBUS Starting at Voltage > vSafe5V (long discharge)	png	10.3. FRS Sequence
10.4	FRS Sequence with VBUS starting at vSafe5V (short or no discharge)	png	10.3. FRS Sequence

Known issues in the source specification

These were transcribed verbatim rather than silently corrected — confirmed against the rendered PDF pages, not just the text layer:

• 3.5. "Sink with Acessory Support" — "Accessory" is misspelled in both the printed Table of Contents and the section heading itself (page 47).
• Table 3.3 and Table 3.7 body text — both read "the SPR Source Capabilities = advertised based on Port Present PDP from Table 3.2", using = where "as" is clearly intended. The identical wording in both places suggests one blurb was copy-pasted with the error already present.
• Figure 5.25 / Figure 5.26 mismatch — Section 5.3.4.9 body text says "Figure 5.26, 'Inter-Frame Gap Timings' illustrates the inter-Frame gap timings", but the actual figure a few lines later is captioned "Figure 5.25. Inter-Frame Gap Timings". There is no Figure 5.26 anywhere in the chapter.
• Table 4.6 dangling footnote marker — the cSrcBulkShared row (page 79) carries a footnote marker [^1] in the PDF, but no corresponding footnote text appears anywhere else on that page or through the end of the chapter (page 84). The marker is preserved in the transcription; there is no footnote text to add.
• Page 285, "Shallnotify" — Section 9.2.3.6 (PE_SRC_Ready State) prints "the Source Shallnotify the Protocol Layer of the end of the Atomic Message Sequence" — the space between "Shall" and "notify" is missing in the PDF itself. Preserved verbatim.
• Appendix B duplicate/inconsistent contributor entries — the same organization appears twice under slightly different names, as separate headings with different contributor lists under each: "Bizlink Technology Inc." and "Bizlink Technology, Inc."; "LG Electronics Ltd." and "LG electronics"; "ROHM Co., Ltd." and "Rohm Co. Ltd.".

Tool notes

• This specification prints each figure's Figure N.M. Caption line above the figure rather than below it (the opposite of the Renesas datasheet template tools/extract-figures.py was originally written for). The tool was extended with a --caption-position {above,below} flag and decimal figure numbers (4.1, not zero-padded integers) to support this document; above was used throughout. It also now requires the caption line to be bold, to avoid matching plain-prose sentences like "Figure 4.2 illustrates the application of..." as a caption.
• Figure 7.3 ("Illustration of process to enter EPR Mode") has an explanatory sentence sandwiched between its caption and the actual diagram, which defeated the automatic body-text lower-bound detection (the sentence itself was mistaken for the end of the figure, leaving an empty band). It was cropped with an explicit --region '26:54,104,558,690:figure-7.3.png' against 07-pd-communications-protocol-message-usage.pdf.